CMOS output buffer circuit which converts CMOS logic signals to

Details CMOS output buffer circuit which converts CMOS logic signals to CMOS output buffer circuit which converts CMOS logic signals to

1996-06-20

1998-05-12

Westin, Edward P.

Electronic digital logic circuitry

Interface

Logic level shifting

326 83, H03K 190175, H03K 19094

Patent

active

057511675

ABSTRACT:
Delay time characteristics of rise time and fall times of an output in a CMOS output buffer converting CMOS logic signals into ECL logic signals are made coincident with each other to eliminate various kinds of bias-voltage power supplies required for discharging the charge of capacitance parasitically present on an output-side. The amplifier 1 amplifies an input and supplies a driving input for an outputting P-channel MOSFET 2. A bypass control circuit 4, which inputs gate signals 1001 from the amplifier 1 and a drain potential of the outputting P-channel MOSFET 2 from an output terminal 105, acts as a NAND circuit of those two inputs, and feeds gate signals 1002 so as to cause conduction of the bypassing P-channel MOSFET only at a transient period during which a "high" level outputted to the output terminal 105 is converted into a "low" level, thus the charge on a load capacitance parasitically arisen on the output terminal 105 side is discharged.

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