CMOS off chip driver for fault tolerant cold sparing

Details CMOS off chip driver for fault tolerant cold sparing CMOS off chip driver for fault tolerant cold sparing

1990-10-16

1992-05-26

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307473, 3072962, 3072965, 307270, 307584, H03K 19092, H03K 1716

Patent

active

051171295

ABSTRACT:
A full swing CMOS logic circuit provides fault tolerant, cold sparing of VLSI logic devices attached to a high speed bus. P-channel FET transistors are formed in an N-well which has a biasing transistor which effectively decouples the circuit when the circuit is not powered. The input/output interface of the cold spares have a high impedance and do not corrupt an interconnected electronic bus. The final drive transistors are reverse biased or clamped to zero to prevent any leakage paths.

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