CMOS N-well bias generator and gating system

Details CMOS N-well bias generator and gating system CMOS N-well bias generator and gating system

1985-06-21

1987-06-02

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Semiconductive

365182, 365226, G11C 700, G11C 1300

Patent

active

046708618

ABSTRACT:
A system for preventing forward biasing of the bit line junctions formed between the N-well and bit lines of a CMOS memory. The system includes a gating system for maintaining the bit line voltage at V.sub.CC /2 whenever the well voltage is less than V.sub.CC. A well regulator and well pump maintain the well voltage at a selected multiple of V.sub.CC.

REFERENCES:
patent: 4233672 (1980-11-01), Suzuke
patent: 4356412 (1982-10-01), Moench et al.
patent: 4472792 (1984-09-01), Shimohigashi et al.
patent: 4532439 (1985-07-01), Koike
An N-Well CMOS Dynamic RAM by Shimohigashi et al, IEEE Journal of Solid State Circuits, vol. SC-17, No. 2, Apr. 1982.
An 8K.times.8 Bit Static MOS RAM Fabricated by nMOS
Well CMOS Technology by Ohzone et al. IEEE Journal Solid State Ccts., vol. SC-15, No. 5, Oct./80.
1983 IEEE Intnl. Solid State Circuits Conference, Session 6, A 70ns High Density CMOS-DRAM.

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