CMOS-microprocessor chip and package anti-resonance apparatus

Details CMOS-microprocessor chip and package anti-resonance apparatus CMOS-microprocessor chip and package anti-resonance apparatus

2001-01-04

2002-11-19

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S083000, C326S026000

Reexamination Certificate

active

06483341

ABSTRACT:

BACKGROUND
As microprocessor circuits have achieved greater and greater speeds, these circuits have become more and more sensitive to the effects of parasitic inductance. The parasitic inductance can come from such sources as bond wires, IC package leads, and external supply lines that provide operating power. The problem with such characteristics is that they form a very high supply line impedance at the resonance frequency. This may lead to circuit oscillation
10
as shown in FIG.
1
. In order to avoid such undesirable effects on circuit operation, the inductance must be suitably controlled.
Prior art methods of controlling parasitic inductance include connecting an external capacitor between the supply leads. This connection creates a passive bypass that decreases the supply line oscillation due to external inductances. However, it does not significantly reduce the oscillation caused by internal inductances. Another prior method includes connecting on on-chip capacitor between the internal supply leads. The capacitor acts as a bypass in the same manner as an external capacitor. The resulting non-oscillating circuit performance is shown in FIG.
2
. However, in order to be effective, the internal capacitor must be very large. This has the drawback of occupying a significant portion of the chip area. Consequently, this method is generally undesirable when minimization of the die area is of great importance.
Another prior art approach involves increasing the amount of charge stored or delivered to a given amount of added on-chip de-coupling capacitance by actively increasing the voltage variation across their terminals.
FIG. 3
shows a schematic of this technique with resistance losses. In this method, fully charged capacitors
32
and
34
of equal value are stacked in series
36
across the on-chip Vdd/Vss grid. The capacitors serve as a voltage multiplier for the Vdd/Vss grid. The depleted voltage in each capacitor is Vdd
, where n is the number of capacitor stacks. Conversely, the stacked capacitors will store charge from the Vdd/Vss grid until the terminals across the capacitors are fully at Vdd.
A capacitance amplification factor (G) represents the charge supplied to the grid by the switched capacitors normalized to the charge furnished by regular de-coupled capacitors given the same supply voltage variation. The amplification can be expressed as G=(k+n−1)/(k*n
2
), where n is the number of stacks and k is the voltage regulation tolerance. With each capacitor having a value (Cd), the equivalent unstacked capacitance of Cd*n is reduced to Cd
upon stacking with a total stack voltage of Vdd*n.
FIG. 4
a
shows a schematic
40
of an implementation of the method. The circuit shows mutually exclusive CMOS switches the configure the capacitors (C
1
)
50
and (C
2
)
52
to either be in the charging phase (shunt across Vdd/Vss) or in the discharging phase (in series with Vdd/Vss). The circuit has two sections: the V
ave
(average voltage) tracking loop
42
and the V
inst
(instant voltage) monitor and charge pump loop
44
. The switches are driven by two complementary driver
46
and
48
. These drivers each provide 2 outputs with enough voltage offset to ensure minimal leakage through both charge and discharge switches during switching activity.
Instantaneous voltage supply variation (V
inst
) is monitored by coupling the Vdd and Vss onto a comparator
48
input that is dynamically biased about a reference voltage (V
ave
). V
ave
is a high-pass filtered version of the local ((Vdd−Vss)/2. Its low frequency cutoff clears the low end resonance range, but it also rejects the tracking of low-frequency disturbances that are not due to resonance. The coupled V
inst
feed the main negative feedback loop as charge is pumped in and out of the switched capacitors
50
and
52
coupled to the Vdd/Vss grid in an attempt to defeat the voltage variations. The compensated high frequency cutoff ensures stable loop response while also clearing the high end of the resonance range.
FIG. 4
b
shows the operation
54
of the circuit shown in
FIG. 4
a
. Specifically, the graph shows: a steady state when V
inst
=V
ave
; a discharging phase when V
inst
<V
ave
; and a charging phase when V
inst
<V
ave
. The high frequency and low frequency cutoffs are also shown for their respective phases.
While the method of using stacked capacitors has been demonstrated to be effective in minimizing the effect of parasitic inductance, space is at a premium in microprocessor design. Any method of obtaining the same performance while reducing the required area on the chip yields significant cost benefits.
SUMMARY OF INVENTION
In some aspects the invention relates to an apparatus for regulating resonance in a micro-chip comprising: at least one on-chip de-coupling capacitor, the capacitor connected across a micro-chip supply voltage and a micro-chip ground voltage; and a band-pass shunt regulator connected in parallel with the capacitor across the micro-chip supply voltage and the micro-chip ground voltage, wherein the shunt regulator shorts the supply voltage and the ground voltage at a pre-determined frequency.
In an alternative embodiment, the invention relates to an apparatus for regulating resonance in a micro-chip comprising: at least one on-chip de-coupling capacitor, the capacitor connected across a micro-chip supply voltage and a micro-chip ground voltage; and means for shorting the supply voltage and ground voltage at a pre-determined frequency.


REFERENCES:
patent: 4893212 (1990-01-01), Wong et al.
patent: 5049764 (1991-09-01), Meyer
“An On-chip Voltage Regulator Using Switched Decoupling Capacitors”, by Michael A. Ang, Raoul B. Salem and Alexander D. Taylor of Sun Microsystems Inc.; presented by Michael A. Ang at 2000 IEEE International Solid-State Circuits Conference, Feb. 7-9, 2000, San Francisco,CA (15 pages).

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