CMOS memory cell with improved read port

Details CMOS memory cell with improved read port CMOS memory cell with improved read port

1997-07-08

1999-04-13

Nelms, David

Static information storage and retrieval

Systems using particular element

Flip-flop

36523005, G11C 1100

Patent

active

058944320

ABSTRACT:
A memory cell with multiple read ports uses fewer NMOS devices, has reduced size, and provides improved performance if less than all of the read ports are used. The memory cell has a flip-flop with a storage node, a write port, and a read port having a plurality of bit lines connected to respective NMOS transistors which are controlled by respective read wordlines, and these NMOS transistors are coupled to ground via one or more additional NMOS transistor whose gates are connected to the storage node. The width of the latter NMOS transistors is larger than the width of the former transistors which are connected to the bit lines. For example, there might be three bitlines connected respectively to three of the first NMOS transistors, which are further connected to only one second NMOS transistor, wherein the second NMOS transistor is about three times as wide as any one of the three first NMOS transistors. The read port provides improved performance if less than all of the read ports are used due to the stronger conduction of the common NMOS device.

REFERENCES:
patent: 4169233 (1979-09-01), Haraszti
patent: 4480320 (1984-10-01), Naiff
patent: 4545033 (1985-10-01), Naiff
patent: 4592021 (1986-05-01), Suzuki et al.
patent: 5629901 (1997-05-01), Ho
patent: 5642325 (1997-06-01), Ang
patent: 5717638 (1998-02-01), Kim

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