CMOS memory arrangement with reduced data line compacitance

Details CMOS memory arrangement with reduced data line compacitance CMOS memory arrangement with reduced data line compacitance

1985-01-07

1987-01-13

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Differential sensing

365190, 365200, G11C 700

Patent

active

046369880

ABSTRACT:
A CMOS memory arrangement having each of a plurality of data lines connected to a plurality of bitlines, at least one of said datalines having a lesser number of bitlines in order to decrease capacitance in slower signal paths and thereby increase the operating speed of the memory. A multiple input sense amplifier is connected to the plurality of data lines.

REFERENCES:
patent: 4160275 (1979-07-01), Lee et al.
patent: 4270190 (1981-05-01), Jindra et al.
patent: 4435789 (1984-03-01), Giebel et al.
Chan, "Bit-Select Sense Amplifier", IBM Technical Disclosure Bulletin, vol. 24, No. 11A, Apr. 1982, pp. 5654-5656.

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