CMOS memory arrangement

Details CMOS memory arrangement CMOS memory arrangement

1985-01-07

1986-12-02

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

For complementary information

365203, G11C 700

Patent

active

046270310

ABSTRACT:
CMOS memory arrangement including a circuit for setting the dataline voltage at a predetermined bias level, the circuit comprising four MOS transistors, the first, second and third and the first and fourth thereof being connected in respective series from VCC to ground, the gates of the first and second transistors being connected to ground, the bias level being established between the second and third transistors with the gate of the third transistor being connected to the node therebetween.

REFERENCES:
patent: 4160275 (1979-07-01), Lee et al.
patent: 4270190 (1981-05-01), Jindra et al.
patent: 4435789 (1984-03-01), Giebel et al.
patent: 4451907 (1984-05-01), Donoghue et al.
Chan, "Bit Select Sense Amplifier", IBM Technical Disclosure Bulletin, vol. 24, No. 11A, Apr. 1982, pp. 5654-5656.

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