CMOS lock detect with double protection

Details CMOS lock detect with double protection CMOS lock detect with double protection

2000-08-07

2004-07-06

Corrielus, Jean B. (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S376000, C331SDIG002, C331S025000, C327S156000, C327S159000

Reexamination Certificate

active

06760394

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device for monitoring the frequency discrepancy between two signals in conjunction with at least one data signal so as to improve the accuracy and efficiency of a phase-locked loop.
A phase-locked loop (PLL) is a circuit that is capable of synchronizing an output signal generated by an oscillator with a reference or input signal in frequency as well as in phase.
FIG. 1
shows a simplified block diagram of the functional elements of a conventional PLL. A conventional PLL generally includes a voltage-controlled oscillator (VCO)
10
, a phase detector
12
, and a loop filter
14
. A PLL uses feedback to maintain an output signal in a specific phase with a reference signal. The VCO
10
generally oscillates at an angular frequency which is determined by the output signal
20
of the loop filter
14
which, in turn, is controlled by the output signal
18
of the phase detector
12
. In turn, the output
22
of the VCO
10
and the external reference or input signal
16
dictate the output signal
18
of the phase detector
12
. Hence, if the phase error between the VCO output
22
and the external reference or input signal
16
is not zero or within a tolerable margin, the phase detector
12
will develop a nonzero output
18
, thereby via the loop filter
14
causing the VCO
10
to produce an output signal
22
that is synchronized or locked with the external reference or input signal
16
and reducing the phase error to an acceptable level.
The process of achieving a lock between the VCO output
22
and the external reference or input signal
16
involves two steps. First, the frequencies of the two signals
16
,
22
have to be matched. When the two frequencies are matched, the two signals
16
,
22
are sometimes referred to as being in a frequency-locked mode. Once the frequency-locked mode is achieved, the phases of the two signals
16
,
22
are then matched thereby achieving a phase-locked mode. In other words, the frequency-locked mode is a prerequisite to achieving the phase-locked mode. Once the phase-locked mode is achieved, the PLL can then perform its intended functions.
PLLs are used in many applications including frequency synthesis, modulation, demodulation, and data and clock recovery. For example, in digital communications, it is frequently necessary to extract a coherent clock signal from an input data stream. A PLL is often used for this task by locking a VCO output to the input data stream. Once locked, the VCO output is essentially the clock signal of the input data stream and thus can then be used to extract the data bits from the input data stream.
Quite often, however, two signals for a variety of reasons may disengage from the phase-locked mode. This can happen when the two signals are no longer in frequency-locked mode. For example, when a data signal becomes jittery or disappears entirely, the frequencies of the data signal and the VCO signal can no longer match, thereby causing the two signals to disengage from the frequency-locked mode and subsequently from the phase-locked mode. Therefore, it would be desirable to provide a method and device that is capable of reliably detecting whether two signals are in frequency-locked mode thereby ensuring that the phase-locked mode is maintained.
In addition, different systems often require different degrees of precision to achieve a frequency-locked mode depending on the purposes of the systems. Some systems may require two signals to be closely matched before a frequency-locked mode is considered achieved, while others may permit a wider margin of matching. Therefore, it would be desirable to provide a method and device that is capable of having an adjustable threshold for determining whether a frequency-locked mode is achieved.
Further, as mentioned above, before a PLL can perform its intended functions, it must be engaged in a phase-locked mode first which, in turn, requires as a prerequisite a frequency-locked mode to be achieved. Conversely, a phase-locked mode is disengaged when the prerequisite frequency-locked mode is no longer present. Any unnecessary or mistaken disengagement of the frequency-locked mode thus disrupts the phase-locked mode and consequently prevents the PLL from performing its intended functions. Therefore, it would be desirable to provide a method and device that is capable of efficiently monitoring the activation of the frequency-locked mode so as to optimize the continued operation of a PLL.
Moreover, very often when a PLL is engaged in a phase-locked mode and no data is available for detection, the VCO signal tends to drift and eventually will no longer be considered to be in frequency-locked mode with the external reference or input signal. During this period when the frequency-locked mode is lost, a PLL is not capable of detecting incoming data and such data are thus lost. When this occurs, the phase-locked mode has to be disengaged so as to allow the frequency-locked mode to be reestablished so that as soon as data is available, the PLL can switch to the phase-locked mode to capture the data. Therefore, it would be desirable to provide a method and device that is capable of efficiently monitoring and controlling the transition between the phase-locked mode and the frequency-locked mode so as to minimize data loss. The present invention satisfies the above as well as other needs.
SUMMARY OF THE INVENTION
The present invention seeks to efficiently control the transition between the phase-locked mode and the frequency-locked mode during the operation of a PLL. In one embodiment of the present invention, two counters are used to check the frequency differential between a VCO signal and an external reference or input signal. The external reference or input signal and the VCO signal are used to drive the two counters respectively. Both counters conduct count-downs in a cyclic manner. When the first counter arrives at an identifiable position in its count-down, the second counter is directed to begin its count-down from a predetermined position. When the first counter once again reaches the same identifiable position, the output of the second counter is checked to determine the differential between such output and the identifiable position of the first counter. Such differential can be selectively interpreted to provide an adjustable threshold to determine whether the frequencies of the two signals are considered to be in a frequency-locked mode.
The result of the frequency differential check is propagated through a pair of flip-flops. The pair of flip-flops are connected in series. Hence, the pair of flip-flops records the results of any two consecutive frequency differential checks.
The outputs of the two flip-flops are logically combined to a logic element which produces a low signal when both outputs of the flip-flops are high. In one exemplary implementation, a NAND logic function is provided to accept the output signals of the pair of flip-flops. The NAND logic function produces a low signal only when the results of both frequency differential checks are high, meaning that remedial action should be taken to rectify the frequency-locked mode. This provides the advantage that erroneous detection of a frequency discrepancy is minimized. This also provides the advantage that the PLL is given additional time to pull in the locked frequency when the PLL switches from the frequency-locked mode to the phase-locked mode.
In addition, a data present signal is logically combined with the output of the NAND logic function. An AND logic function, for example, produces a high signal only when both the data present signal and the output of the NAND logic function are high, meaning that data are present for detection and there is no frequency discrepancy. This, in turn, signifies that the phase-locked mode should be maintained. This minimizes unnecessary transition between the phase-locked mode and the frequ

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