CMOS level shifter with steady-state and transient drivers

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction

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Details

326 27, 326 68, 326 98, H03K 190185

Patent

active

057810265

ABSTRACT:
A level shifter is provided with first and second steady-state drivers and transient driver circuitry. Each steady-state driver includes a low enable input, a high enable input and an output. Each steady-state driver outputs from its respective output a low voltage level signal when an enabling voltage level is received at its low enable input and a disabling voltage is received at its high enable input. Furthermore, each steady-state driver outputs from its output a first high voltage level signal, that is higher than a second high voltage level of an input signal, when a disabling voltage level is received at its low enable input and an enabling high voltage level is received at its high enabling input. The high enable input of the first steady-state driver is connected to the output of the second steady-state driver. The high enable input of the second steady-state driver is connected to the output of the first steady-state driver. The input of the first steady-state driver receives a complement of the input signal and the input of the second steady-state driver receives the input signal. The transient driver circuitry responds to a transition in the voltage level of the input signal by driving the output of one of the first and second drivers, to the first high voltage level, for a certain time period. The transient driver circuitry is enabled to drive the output with a maximum driving capacity throughout the aforementioned certain time period.

REFERENCES:
patent: 4504747 (1985-03-01), Smith et al.
patent: 4948991 (1990-08-01), Schucker et al.
patent: 5239237 (1993-08-01), Tran et al.

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