CMOS level conversion circuit with input protection

Details CMOS level conversion circuit with input protection CMOS level conversion circuit with input protection

1995-05-05

1996-02-27

Westin, Edward P.

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 9, 326 83, H03K 190948, H03K 190185

Patent

active

054951852

ABSTRACT:
The current paths of the P-channel transistor, P-channel transistor, and N-channel transistor are connected in series between the power source V.sub.DD and the ground. The inverter circuit is constituted by the transistors. The node of the inverter circuit is connected to an end of the current path of the N-channel transistor. Another end of the current path of the N-channel transistor is connected to the input node. The transistors are of the enhancement type. If the electric potential higher than the power source V.sub.DD is supplied to the input node, the voltage of the node is lower than that of the power source V.sub.DD by the threshold voltage (V.sub.THN) and the transistors are protected from destruction.

REFERENCES:
patent: 4760279 (1988-07-01), Saito et al.
patent: 4825106 (1989-04-01), Tipon et al.
patent: 5036232 (1991-07-01), Jungert et al.
patent: 5095229 (1992-03-01), Yun et al.
patent: 5136186 (1992-08-01), Trinh et al.
English Abstract of Japanese Publication No. 2-283123.

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