Static information storage and retrieval – Systems using particular element – Flip-flop
Patent
1998-09-23
2000-02-15
Nelms, David
Static information storage and retrieval
Systems using particular element
Flip-flop
36518905, 327210, 327211, G11C 1100
Patent
active
060260114
ABSTRACT:
A CMOS latch circuit comprises a data input node, an output node, and first and second inverters, each of which have an input coupled to the data input node, and an output coupled to the output node. Pairs of feedback NFETs and PFETs are each coupled in series between V.sub.CC and ground. Intermediate nodes between each of the NFET and PFET feedback pairs are coupled to the data input node. The gate of the first feedback NFET is coupled to the data input node, and the gate of the second NFET is coupled to the output node. Similarly, the gate of the first PFET is coupled to the output node, and the gate of the second PFET is coupled to the data input node. The CMOS latch circuit maintains a logic state at the output node regardless of a high-energy particle strike.
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Auduong Gene N.
Intel Corporation
Nelms David
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