CMOS inverter and standard cell using the same

Details CMOS inverter and standard cell using the same CMOS inverter and standard cell using the same

1999-06-15

2001-06-26

Hoang, Huan (Department: 2818)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S122000, C326S081000, C257S204000

Reexamination Certificate

active

06252427

ABSTRACT:

DETAILED DESCRIPTION OF THE INVENTION
1. Field of the Invention
The present invention relates to a CMOS inverter including p- and n-channel MOS transistors, and a standard cell using the same.
2. Prior Art
In recent years, the number of devices integrated within a single semiconductor large-scale integrated circuit (LSI) has increased by leaps and bounds. Thus, in laying out an LSI, it has become a commonplace to work out an overall design for the LSI by designing a complicated logic circuit using at least one of standard functional circuit blocks often used, which have been registered as standard cells. A standard cell is a combination of logical elements such as NAND and NOR gates, and a basic cell of each logical element is an inverter. Among various types of inverters, a CMOS inverter is particularly advantageous in low power dissipation. Accordingly, a CMOS inverter is widely used as a basic cell in a standard cell.
FIG. 5
is a circuit diagram of a CMOS inverter including p- and n-channel MOS transistors Tr
1
and Tr
2
. An input signal is supplied in common to the respective gates of the p- and n-channel MOS transistors Tr
1
and Tr
2
, and an output signal is sent out through the commonly connected drains of the p- and n-channel MOS transistors Tr
1
and Tr
2
.
FIG. 6
illustrates a planar structure of a conventional CMOS inverter. A power line
101
for supplying a power supply voltage V
DD
is connected to the source of the p-channel MOS transistor Tr
1
via a first contact
102
. A ground line
103
for supplying a ground voltage V
SS
is connected to the source of the n-channel MOS transistor Tr
2
via a second contact
104
. An output signal line
105
for outputting an output signal V
out
from the CMOS inverter is connected to the respective drains of the p- and n-channel MOS transistors Tr
1
and Tr
2
via third and fourth contacts
106
and
107
, respectively. An input signal line
108
for inputting an input signal V
in
to the CMOS inverter is connected to the respective gate electrodes
109
of the p- and n-channel MOS transistors Tr
1
and Tr
2
via fifth and sixth contacts
110
and
112
, respectively.
In this case, the power line
101
, ground line
103
, output signal line
105
and input signal line
108
are made of aluminum or an aluminum alloy. The power, ground and output signal lines
101
,
103
and
105
are connected to the source or drain of the p- or n-channel MOS transistor Tr
1
or Tr
2
, which is formed on the surface of a semiconductor substrate, via a refractory metal such as tungsten for the first, second, third or fourth contact
102
,
104
,
106
or
107
. The input signal line
108
is connected to the gate electrodes
109
of polysilicon via a refractory metal like tungsten for the fifth or sixth contact
110
or
112
.
PROBLEMS TO BE SOLVED BY THE INVENTION
In a recent advanced LSI with increased density and number of devices integrated, functional elements and interconnects have been miniaturized as much as one possibly can during laying out the LSI to minimize an increase in chip area. Also, the larger the number of devices integrated, the longer the signal propagation delay on the interconnects, thus interfering with an even higher speed operation of an LSI.
Considering the circumstances such as these, some people began to suggest replacing aluminum, which had heretofore been used as a primary interconnect material because of its excellent processability and stability, with copper with lower electrical resistance (which is less easy to process than aluminum, though).
FIG. 7
illustrates a planar structure of a CMOS inverter designed in response to such a demand. Thanks to the improvement in alignment accuracy, the line width of a portion of a metal interconnect to be connected to a contact is substantially equalized with the width of the contact, so that the CMOS inverter can be downsized. And the metal interconnects are made of copper or a copper alloy.
A high-density LSI was modeled using a CMOS inverter with the structure shown in
FIG. 7
as a basic cell, and the reliability thereof was tested. As a result, an interconnection failure, resembling a void formed due to electromigration in a conventional interconnection structure, was also spotted in the interconnection portion of the CMOS inverter. It was also found that in a standard cell composed of a plurality of CMOS inverters, the interconnection failure in the CMOS inverter on the last stage was remarkable.
It was known that electromigration often happens in a long interconnect with a high current density, i.e., a power line, for example. But it was not expected that electromigration should happen in an interconnection region of a CMOS inverter where each line is short and a current density is low. In addition, a copper line was generally believed to be more resistant to electromigration that an aluminum line. Accordingly, it was totally unexpected that a CMOS inverter with the structure shown in
FIG. 7
should get involved with the problem of electromigration.
A defective interconnection region of a last-stage CMOS inverter in a standard cell was observed in detail. As a result, it was found that a void had been formed in an interconnection region near a contact to be connected to the source or drain of the p- and n-channel MOS transistors Tr
1
and Tr
2
as shown in FIGS.
8
(
a
) and
8
(
b
). Specifically, large voids were formed in the power line
101
near the first contact
102
connected to the source of the p-channel MOS transistor Tr
1
and in the output signal line
105
near the fourth contact
109
connected to the drain of the n-channel MOS transistor Tr
2
.
The present inventors looked into the reasons why the voids had been formed only at particular sites in metal interconnects. As a result, we arrived at the following findings.
First, the operating principle of a CMOS inverter will be considered. Referring to the circuit diagram shown in
Figure 5
, if the input signal V
in
is high, then the output signal V
out
is low, because the p-channel MOS transistor Tr
1
turns OFF but the n-channel MOS transistor Tr
2
turns ON. On the other hand, if the input signal V
in
is low, then the output signal V
out
is high, because the p-channel MOS transistor Tr
1
turns ON but the n-channel MOS transistor Tr
2
turns OFF. While the input signal V
in
is stabilized at either high or low level, one of the p- and n-channel MOS transistors Tr
1
and Tr
2
is always OFF. Accordingly, no current flows between the power line
101
and the ground line
103
.
However, at the instant the output signal V
out
changes from low into high, a current flows from the power line
101
toward the output terminal
105
a
of the output signal line
105
via the p-channel MOS transistor Tr
1
as indicated by the arrow A in FIG.
7
. On the other hand, at the instant the output signal V
out
changes from high into low, a current flows from the output terminal
105
a
of the output signal line
105
toward the ground line
103
via the n-channel MOS transistor Tr
2
as indicated by the arrow B in FIG.
7
. That is to say, the current flows bidirectionally between a branch point
105
b
and the output terminal
105
a
in the output signal line
105
, but only unidirectionally between the third contact
106
and the branch point
105
b
and between the fourth contact
107
and the branch point
105
b.
In general, as is well known, when a current flows through a metal interconnect, metal atoms, constituting the metal interconnect, receive the momentum of electrons and move, and a void is formed by the expansion of vacancies, from which the metal atoms have moved. Thus, it is known that electromigration happens in an interconnection region where current flows only unidirectionally, but rarely happens in a region where current flows bidirectionally.
According to the operating principle of the CMOS inverter, the current flows only unidirectionally between the third contact
106
and the branch point
105
b
and between the fourth contact
107
and the branch point
105
b
. In other words,

Affiliated with

Also associated with

Rating

CMOS inverter and standard cell using the same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS inverter and standard cell using the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS inverter and standard cell using the same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2448942