Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Decoding
Reexamination Certificate
2002-03-11
2004-09-21
Than, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Decoding
C326S033000, C326S088000
Reexamination Certificate
active
06794905
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a CMOS inverter and, more particularly, to a CMOS inverter capable of operating at high speeds at low power supply voltages.
2. Description of the Related Art
A CMOS circuit of related art uses a CMOS inverter as shown in FIG.
5
. In this CMOS inverter shown in
FIG. 5
, the source of a p-channel MOS transistor p
1
is connected with a power supply terminal VDD of 3 V, for example. The source of an n-channel MOS transistor n
1
is connected with a power supply terminal VSS that is at ground potential of 0 V. Their gates are connected with an input terminal in. Their drains are connected with an output terminal out. In this way, the circuit is configured.
In the CMOS inverter shown in
FIG. 5
, the threshold voltage Vth of each transistor is an impediment to lower supply voltage operation. In particular, as the power supply voltage drops, the voltage difference between the threshold voltage Vth and an input signal applied to the gate decreases, thus reducing the drain current of each MOS transistor. This reduces the operating speed of the CMOS inverter. In the worst case, it cannot be operated.
It is also contemplated to adjust the threshold voltage Vth of the MOS transistor by the process. However, the process is specialized and so the process sequence is complicated. As a result, the obtained CMOS inverter is more disadvantageous than those fabricated by normal CMOS processes in terms of reliability and cost.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a CMOS inverter that can be easily realized by a manufacturing process and can be operated at lower voltages.
A CMOS inverter of the present invention comprises: a p-channel MOS transistor having a source connected with a first power supply terminal; an n-channel MOS transistor having a source connected with a second power supply terminal that is at a lower potential than the first power supply terminal; an output terminal connected with the junction of the drain of the p-channel MOS transistor and the drain of the n-channel MOS transistor; a first capacitor having one terminal connected with the gate of the p-channel MOS transistor and the other terminal connected with an input terminal; a second capacitor having one terminal connected with the gate of the n-channel MOS transistor and the other terminal connected with the input terminal; a first voltage source for producing a first bias voltage applied to the gate of the p-channel MOS transistor; and a second voltage source for producing a second bias voltage applied to the gate of the n-channel MOS transistor.
Another CMOS inverter of the invention comprises: a first p-channel MOS transistor having a source connected with a first power supply terminal; a first n-channel MOS transistor having a source connected with a second power supply terminal that is at a lower potential than the first power supply terminal; an output terminal connected with the junction of the drain of the first p-channel MOS transistor and the drain of the first n-channel MOS transistor; a first capacitor having one terminal connected with the gate of the first p-channel MOS transistor and the other terminal connected with an input terminal; a second capacitor having one terminal connected with the gate of the first n-channel MOS transistor and the other terminal connected with the input terminal; a first resistor having one terminal connected with the gate of the first p-channel MOS transistor and the other terminal connected with the junction of the gate and drain of the second p-channel MOS transistor; a second resistor having one terminal connected with the gate of the first n-channel MOS transistor and the other terminal connected with the junction of the gate and drain of the second n-channel MOS transistor; a third resistor connected between the drain of the second p-channel MOS transistor and the second power supply terminal; a fourth resistor connected between the drain of the second n-channel MOS transistor and the first power supply terminal; a third p-channel MOS transistor having its gate and drain connected together, the source of the third p-channel MOS transistor being connected with the first power supply terminal, the drain of the third p-channel MOS transistor being connected with the source of the second p-channel MOS transistor; and a third n-channel MOS transistor having its gate and drain connected together, the source of the third n-channel MOS transistor being connected with the second power supply terminal, the drain of the third n-channel MOS transistor being connected with the source of the second n-channel MOS transistor.
REFERENCES:
patent: 4794283 (1988-12-01), Allen et al.
patent: 6072353 (2000-06-01), Matsuzawa
patent: 6351138 (2002-02-01), Wong
Isobe Masayoshi
Sato Masatoshi
Nippon Precision Circuits Inc.
Than Anh Q.
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