CMOS integrated circuit with EEPROM and method of manufacture

Details CMOS integrated circuit with EEPROM and method of manufacture CMOS integrated circuit with EEPROM and method of manufacture

1990-02-26

1991-05-07

Jackson, Jr., Jerome

357 42, 357 233, H01L 2701

Patent

active

050140981

ABSTRACT:
The present invention relates to an integrated circuit which includes complementary MOS transistors (e.g., a CMOS circuit), an EEPROM, and to a method of making the integrated circuit. The EEPROM is incorporated in the circuit in such a manner that it does not adversely affect the high performance, low voltage operation of the CMOS circuit. Also, the EEPROM is designed so that it is programmable at a low voltage which is compatible with the low voltages typically used with the CMOS circuit. The EEPROM includes a floating gate and a control gate which have a large area of overlap so as to provide a high capacitance therebetween. This provides a high ratio (e.g., about two or greater) of the floating gate to control gate capacitance divided by the floating gate to substrate capacitance to provide the EEPROM with the low voltage operation. To make the integrated circuit, standard CMOS process steps using design rules of about two microns or less are used to make the MOS transistors. Additional steps are inserted in the standard CMOS process to form the EEPROM. The additional steps are inserted in such a manner so as not to adversely affect the operating characteristics of the resulting MOS transistors. For this purpose, any additional steps for forming the EEPROM which are carried out at a temperature of greater than 900.degree. C. are done so before the gate silicon dioxide layer of the MOS transistors is formed, and any further steps of forming the EEPROM are carried out at temperatures no greater than 900.degree. C.

REFERENCES:
patent: 4608585 (1986-08-01), Keshtbod
patent: 4701776 (1987-10-01), Perlegos et al.
patent: 4794565 (1988-12-01), Wu et al.

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