CMOS integrated circuit having improved isolation

Details CMOS integrated circuit having improved isolation CMOS integrated circuit having improved isolation

1988-08-30

1991-09-03

Wojciechowicz, Edward J.

357 2312, 357 52, H01L 2978

Patent

active

050458981

ABSTRACT:
A p-type tub in a CMOS integrated circuit is isolated from the adjacent n-type tub by means of a field oxide having a p-type channel stop region formed by a boron ion implant. The depth of the ion implant is selected so that the peak of the boron concentration is located immediately under the field oxide region that is subsequently grown. In addition, the implant is allowed to penetrate into the active device regions, producing a retrograde boron concentration in the n-channel region. This technique simultaneously improves device isolation and n-channel transistor punch-through characteristics, allowing the extension of CMOS technology to sub-micron device geometries.

REFERENCES:
patent: 4354307 (1982-10-01), Vinson et al.
patent: 4554726 (1985-11-01), Hillenius et al.
patent: 4700212 (1987-10-01), Okazawa
patent: 4755863 (1988-07-01), Maeda et al.
patent: 4889825 (1989-12-01), Parrillo
patent: 4903107 (1990-02-01), Wei

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