CMOS integrated circuit device and its inspecting method and...

Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed

Reexamination Certificate

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Details

C438S014000, C257S048000, C324S765010

Reexamination Certificate

active

06187602

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a CMOS integrated circuit device and an inspecting method and an inspecting device thereof.
2. Description of the Prior Art
In general, when the threshold value of a MOSFET is reduced, since the current driving capability of the MOSFET increases, the circuit can operate at high speed, so that it is possible to realize a high performance LSI. On the. other hand, in the case where the supply voltage is reduced to lower the power consumption, it is possible to realize a low power consumption, without decreasing the operation speed, by reducing the threshold value of the MOSFET.
By the way, in the case where a CMOS integrated circuit provided with CMOS circuits having P-channel MOS transistors and N-channel MOS transistors is required to be inspected, there has been widely adopted such an inspection method that a defective CMOS integrated circuit can be selectively rejected by checking the static current of the voltage supply. In this inspection method, after a supply voltage is applied to the CMOS integrated circuit, an H- or L-level signal is given to an input terminal thereof, to measure the current flowing through the voltage supply. In this case, when a large current beyond a predetermined value flows therethrough, the chip is regarded as being mixed with some defective CMOS circuits and thereby selectively rejected. The reason why such method can be used is that the CMOS circuit is provided with such a feature that voltage supply current (a static supply voltage current) does not flow on condition that the input of the CMOS circuit does not change (i.e., in a static status).
In this case, however, when the threshold value of the MOSFET is reduced, since the sub-threshold current of the MOSFET increases and thereby a relatively large static voltage supply current flows even through a non-defective chip, this inspection method cannot be adopted. As a result, there exists such a problem in that the defective chips are erroneously selected and put on the market or that an excessive inspection cost is required to prevent the defective chips from being mixed with the non-defective chips.
SUMMARY OF THE INVENTION
With these problems in mind, therefore, it is the object of the present invention to provide a CMOS integrated circuit device and its inspecting method and device, which can inspect the static current flowing through the voltage supply of the CMOS circuits precisely.
To achieve the above-mentioned object, the first aspect of the present invention provides a CMOS integrated circuit device, comprising: at least one CMOS circuit having at least one P-channel MOS transistor and at least one N-channel MOS transistor; a first pad connected to a source of the P-channel MOS transistor; a second pad connected to a source of the N-channel MOS transistor; a third pad connected to an N-type substrate or an N-type well formed with the P-channel MOS transistor; and a fourth pad connected to a P-type substrate or a P-type well formed with the N-channel MOS transistor.
Further, it is preferable that when shipped, the third pad is so connected that a first supply potential can be applied thereto; and the fourth pad is so connected that a second supply potential can be applied thereto.
Further, the second aspect of the present invention provides a method of inspecting a CMOS integrated circuit device, which comprises the steps of: applying a first supply potential to the first pad; applying a second supply potential lower than the first supply potential to the second pad; applying a supply potential higher than the first supply potential to the third pad; applying a supply potential lower than the second supply potential to the fourth pad; and measuring current flowing through the first or second pad for inspection, to selectively reject the CMOS integrated circuit device.
Further, the third aspect of the present invention provides a method of inspecting a CMOS integrated circuit device, which comprises the steps of: applying a supply potential higher than a first supply potential to the third pad; applying a supply potential lower than a second supply potential to the fourth pad; applying a third supply potential lower than the first supply potential but higher than the second supply potential to the first pad; applying a fourth supply potential lower than the third supply potential but higher than the second supply potential to the second pad, the second supply potential being lower than the first supply potential.
Further, the fourth aspect of the present invention provides a method of inspecting a CMOS integrated circuit device having a P-channel MOS transistor and an N-channel MOS transistor, which comprises the steps of: applying a supply potential higher than that for normal use to an N-type substrate or an N-type well formed with the P-type MOS transistor; and applying a potential lower than that for normal use to a P-type substrate or a P-type well formed with the N-type MOS transistor.
Further, the fifth aspect of the present invention provides a device for inspecting a CMOS integrated circuit device, which comprises: first means for applying a first supply potential to the first pad, and a second supply potential lower than the first supply potential to the second pad; second means for applying a supply potential higher than the first supply potential to the third pad, and a supply potential lower than the second supply potential to the fourth pad; and third means for selectively rejecting the CMOS integrated circuit device on the basis of current flowing through the first or second pad.
Further, the sixth aspect of the present invention provides a device for inspecting a CMOS integrated circuit device as defined by the first aspect, which comprises: first means for applying a supply potential higher than a first supply potential to the third pad, and a supply potential lower than the second supply potential to the fourth pad; and second means for applying a third supply potential lower than the first supply potential but higher than the second supply potential to the first pad, and a fourth supply potential lower than the third supply potential but higher than the second supply potential to the second pad, the second supply potential being lower than the first supply potential.


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patent: 5731700 (1998-03-01), McDonald

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