CMOS integrated circuit device and data processing system using

Details CMOS integrated circuit device and data processing system using CMOS integrated circuit device and data processing system using

1994-01-21

1995-10-03

Westin, Edward P.

Electronic digital logic circuitry

Interface

Logic level shifting

326 47, 326 50, H03K 190175

Patent

active

054555248

ABSTRACT:
A CMOS LSI stably operates with high speed ECL LSI's to provide a data processing system. Two power sources of a negative ECL operation voltage and a positive CMOS operation voltage are provided. In a CMOS LSI, input signals of ECL level are successively amplified through an ECL input interface having a p-channel differential amplifier and an n-channel type differential amplifier, fed to the CMOS output buffer circuit and converted to the CMOS level, processed in a CMOS internal circuit, and output at the ECL level through output open-drain MOSFETs. The CMOS LSI is operated by two power sources which are level-shifted in correspondence with the ECL signal amplitude, instead of using ground potential and a positive voltage such as VDD.

REFERENCES:
patent: 4992681 (1991-02-01), Urakawa
patent: 5045730 (1991-09-01), Cooperman
patent: 5068551 (1991-11-01), Bosnyak
patent: 5216298 (1993-06-01), Ohba
patent: 5264744 (1993-11-01), Mizukami
patent: 5331219 (1994-07-01), Nakamura
ISSC 89, Digest Of Technical Papers, "High-Speed SRAMS", pp. 32-33; Feb. 15, 1989.

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