Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2000-04-03
2001-11-20
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S083000, C326S057000
Reexamination Certificate
active
06320415
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a CMOS input/output control circuit. More particularly, the present invention relates to a CMOS input/output control circuit capable of tolerating a range of voltage inputs.
2. Description of Related Art
FIG. 1
is a schematic diagram of a conventional CMOS input/output control circuit. As shown in
FIG. 1
, the CMOS input/output control circuit
100
comprises a PMOS transistor
10
, an NMOS transistor
20
, a NAND gate
30
, a NOR gate
40
, an inverter
50
, a buffer
60
and an input/output pad
70
.
(1) When the CMOS input/output control circuit
100
functions as an output device, a high potential level is applied to the output enable signal lead. A low potential level appears at the output terminal of the NAND gate
30
and a low potential level appears at the output terminal of the NOR gate
40
. Hence, the PMOS transistor
10
is switched on while the NMOS transistor
20
is switched off. Consequently, the input/output pad
70
is at a high potential level (source voltage V
DD
). Conversely, if a low potential level is applied to the output enable signal lead, a high potential level appears at the output terminal of the NAND gate
30
and the output terminal of the NOR gate
40
. Hence, the PMOS transistor
10
is switched off while the NMOS transistor
20
is switched on. Consequently, the input/output pad
70
has a low potential.
(2) When the CMOS input/output control circuit
100
functions as an input device, a low potential level is applied to the output enable signal lead. Hence, the output terminal of the NAND gate
30
is at a high potential level and the low output enable signal after passing through the inverter
50
to the NOR gate
40
produces a low output potential level. Therefore, both the PMOS transistor
10
and the NMOS transistor are turned off. Consequently, signal to the input/output pad
70
, whether the potential level is high or low, can be relayed to the buffer
60
and become an input signal for any internal circuit.
Under both circumstances, the CMOS input/output control circuit
100
is functional as long as the high potential is at the same level as the source voltage V
DD
. However, since the development of submicron (smaller than 0.15 &mgr;m) VLSI fabrication technologies, required source voltage has dropped from 5 V to 3.3 V or 2.5 V.
FIG. 2
is a schematic cross-sectional view of a conventional CMOS transistor. According to fundamental CMOS processing concept, the n-well
12
must be coupled to the highest voltage level in the circuit. In other words, the n-well of the PMOS transistors must be coupled to the highest voltage. The p-substrate
22
of the NMOS transistor must be coupled to the lowest voltage or ground. The CMOS circuit operates normally within the input/output control circuit only when the aforementioned voltage connections are made.
However, if 5 V are applied to the input/output pad
70
when the source voltage V
DD
is at 3.3 V or 2.5 V, a PN junction current forward bias will flow in the n-well region shown in FIG.
2
. This is because a higher voltage is applied to the input/output pad
70
the source voltage V
DD
. Hence, a leakage current i will flow from the drain terminal to the n-well and then return back to the voltage source V
DD
. Since the PMOS transistor may malfunction, a conventional input/output control circuit may fail when voltage applied to the input/output pad is higher than the source voltage V
DD
.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a CMOS input/output control circuit capable of operating normally under a range of input operating voltages such as 2.5 V, 3.3 V or 5 V.
A second object of this invention is to provide a CMOS input/output control circuit capable of tolerating a range of input voltages. To permit a 5 V input voltage, a gate control circuit and an n-well control circuit are used to turn off the PMOS transistor inside the n-well region of the CMOS input/output control circuit.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a CMOS input/output control circuit capable of tolerating a range of input voltages. The control circuit includes a PMOS transistor, an NMOS transistor, a NAND gate, a NOR gate, an inverter, a buffer, an input/output pad, an n-well control circuit and a gate control circuit. The n-well control circuit is coupled to the n-well of the PMOS transistor and the input/output pad. When an input voltage higher than the source voltage is applied, voltage at the n-well of the PMOS transistor is increased by the n-well control circuit to the source voltage level. The gate control circuit is coupled to the gate terminal of the PMOS transistor and the input/output pad. When an input voltage higher than the source voltage is applied, voltage at the gate terminal of the PMOS gate is increased by the gate control circuit to the source voltage level.
In a second embodiment of this invention, a CMOS input/output control circuit capable of tolerating a range of input voltage is provided. The circuit includes a NAND gate, an inverter, a NOR gate, a PMOS transistor, an NMOS transistor, an input/output pad, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor. One of the input terminals of the NAND gate is an output enable signal terminal. The other input terminal of the NAND gate is an output signal terminal. The input terminal of the inverter is coupled to the output enable signal terminal. One of the input terminals of the NOR gate is an output signal terminal while the other input terminal is coupled to the output terminal of the inverter. The source terminal of the PMOS transistor is coupled to a source voltage. The drain terminal of the PMOS transistor is coupled to the input/output pad. The source terminal of the NMOS transistor is coupled to a low voltage potential. The drain terminal of the NMOS transistor is coupled to the input/output pad. The gate terminal of the NMOS transistor is coupled to the output terminal of the NOR gate. Both the drain terminal and the gate terminal of the first NMOS transistor are coupled to the source voltage. The source terminal of the first PMOS transistor is coupled to the drain terminal of the first NMOS transistor. The drain terminal and n-well of the first PMOS transistor are coupled to the source terminal of the first NMOS transistor as well as the n-well of the PMOS transistor. The gate terminal of the second PMOS transistor is coupled to the source voltage. The source terminal of the second PMOS transistor is coupled to the input/output pad. The drain and the n-well of the second PMOS transistor are coupled to the drain terminal of the first PMOS transistor. The gate terminal of the second NMOS transistor is connected to the source voltage. The source terminal of the second NMOS transistor is coupled to the input/output pad. The drain terminal of the second NMOS transistor is coupled to the gate terminal of the first PMOS transistor. The gate terminal of the third PMOS transistor is connected to the source voltage. The drain terminal of the third PMOS transistor is coupled to the gate terminal of the first PMOS transistor. The n-well of the third PMOS transistor is coupled to the drain terminal of the first PMOS transistor. The source terminal of the third PMOS transistor is coupled to the input/output pad. The n-well of the fourth PMOS transistor is coupled to the drain terminal of the first PMOS transistor. The source terminal of the fourth PMOS transistor is coupled to the output terminal of the NAND gate. The drain terminal of the third NMOS transistor is coupled to the source terminal of the fourth PMOS transistor. The source terminal of the third NMOS transistor is coupled to the drain terminal of
Le Don Phu
Thomas Kayden Horstemeyer & Risley
Tokar Michael
United Microelectronics Corp.
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