Electronic digital logic circuitry – Interface – Logic level shifting
Patent
1997-07-03
1999-12-07
Santamauro, Jon
Electronic digital logic circuitry
Interface
Logic level shifting
326 68, H03K 19175, H03K 19094
Patent
active
059990171
ABSTRACT:
A CMOS implemented output buffer (10) provides ECL level output signals. The output buffer (10) is implemented in two stages. The first stage (36) includes an inverter having a resistor (39) in series with a P-channel transistor (38) and an N-channel transistor (40) and provides the initial buffering. The resistor (39) in the first inverter stage (36) is used to reduce a cross-over current in the second drive stage (42). The second stage (42) provides additional drive capability and includes an integral level converter. The integral level converter is implemented as a P-channel transistor (44) connected in series with the P-channel and N-channel output driver transistors (53 and 55). The P-channel transistor (44) provides the level shifting function to ECL levels for the second stage. The bias level of the P-channel transistor (44) determines the output logic swing.
REFERENCES:
patent: 4384220 (1983-05-01), Segawa et al.
patent: 5117125 (1992-05-01), Mayes
patent: 5361002 (1994-11-01), Casper
patent: 5376843 (1994-12-01), Tien et al.
patent: 5428303 (1995-06-01), Pasqualini
Chang Daniel D.
King Robert L.
Motorola Inc.
Santamauro Jon
Yudell Craig J.
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