CMOS image sensor arrangement with reduced pixel light...

Details CMOS image sensor arrangement with reduced pixel light... CMOS image sensor arrangement with reduced pixel light...

2005-01-04

2005-01-04

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S184000, C257S187000, C257S203000, C257S292000, C257S293000, C257S433000, C257S461000, C257S462000, C257S929000

Reexamination Certificate

active

06838715

ABSTRACT:
An exemplary CMOS image sensor comprises a plurality of pixels arranged in an array. The plurality of pixels includes a first pixel proximate an optical center of the array, and a second pixel proximate a peripheral edge of the array. The CMOS image sensor further comprises a first metal interconnect segment associated with the first pixel situated in a first metal layer, and a second metal interconnect segment associated with the second pixel situated in the first metal layer. The second metal interconnect segment is shifted closer to the optical center of the array than the first metal interconnect segment so that the second metal interconnect segment approximately aligns with a principle ray angle incident the second pixel, thereby reducing pixel light shadowing.

REFERENCES:
patent: 6171885 (2001-01-01), Fan et al.
patent: 6242769 (2001-06-01), Chang et al.

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