Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-11-15
2002-08-13
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S290000, C257S291000, C257S233000, C257S239000, C438S048000
Reexamination Certificate
active
06433373
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a CMOS image sensor, more particularly, to a CMOS image sensor and a fabrication method thereof comprising a photo diode region that is expanded over all the lower portion of an active region where a transfer gate is formed so as to enhance the sensitivity of the sensor and that has different potential level according to a position in the photo diode region.
2. Discussion of the Related Art
Recently, the functions of most electronic productions are versatile. For instance, a personal computer is equipped with a compact disk—read only memory (CD-ROM) driver, a digital versatile disk (DVD) player, or a camera for a video conference. Also, for editing pictures by using a computer, digital cameras attached to computers are commonly for sale. Even a notebook computer and a cellular phone having a small size camera mounted within them will be put in large quantities on a market soon.
Attaching a camera to a large size product like personal computer does not cause any troubles in using it. However, portable products of small size such as a notebook computer or a cellular phone will have serious problems in case of being attached with a camera since a typical product uses a charge coupled device as an image sensor (a photosensitive device). But the charge coupled device (CCD) consumes a large power and therefore a large cell has to be used for the camera.
Most CCD devices that have been already developed are driven by higher voltage (+15 to −9 V) than a CMOS circuit and a fabrication process of the CCD devices are basically similar to a fabrication process of bipolar transistor. Therefore, the cost for fabricating the CCD devices is much higher than the case for the CMOS.
In order to solve a such a problem, a study on implementing and producing CMOS image sensors has been done to realize the CCD image sensors being operated by a low voltage and a low power consumption as well as having a low production cost.
A conventional CMOS image sensor will be described as follows by referring to the accompanying drawings.
FIG. 1
is a cross sectional view of
3
transistor (TR) pixel structure of a conventional CMOS image sensor and
FIG. 2
is a circuit configuration of the
3
TR pixel of the conventional CMOS image sensor.
FIG. 1
shows a cross sectional view of a three transistor pixel structure of a conventional CMOS image sensor. Since a standard CMOS process is conventionally applied to a CMOS image sensor, an n type well
102
is formed in a p type semiconductor substrate
100
to form a light receiving portion.
In order to sense image charges generated in the light receiving portion, a p type well
101
is formed adjacent to said n type well
102
.
A n+ region
103
a
is extended from the surface of the n type well
102
to a portion of the surface of the p type well
101
.
The n+ region
103
a
is used as a channel to move the image charges. An n+ region
103
b
is formed in a portion of the surface of the p type well region
101
spaced apart from the n+ region
103
a
and is used as a floating region in which sensing operation for the image charges is performed.
Next, a transfer gate
104
for transferring the charges is formed over the substrate between the n+ region
103
a
and the n+ region
103
b.
FIG. 2
shows a circuit configuration of a three transistor (TR) pixel structure of a conventional CMOS image sensor. The circuit of
3
TR pixel structure is constructed with a reset transistor
1
, a select transistor
4
and an access transistor
7
.
The reset transistor
1
has a gate to receive a reset signal through a signal input terminal
2
, one electrode connected to a floating node
5
and the other electrode connected to a VDD terminal
3
. The select transistor
4
has a gate connected to the floating node
5
and one electrode connected to the VDD terminal
3
. The other electrode of the select transistor
4
is connected to the access transistor
7
. The access transistor
7
is connected in series between the select transistor
4
and a column select line
9
. The gate of the access transistor
7
is connected to a row select signal input terminal
8
so as to receive a row select signal. A photo diode
6
is connected between said floating node
5
and a ground terminal
10
.
The sensing operation of the
3
TR of the conventional CMOS image sensor is described as follows.
Image charges that are induced by incident light from outside to a photo diode
6
are accumulated in the photo diode
6
. The accumulated signal charges therein change a potential of the floating node
5
which is used as a source terminal of the reset transistor
1
and therefrom change the gate potential of the select transistor
4
which is used as a driver of a pixel level source follower. The change of the gate potential of the select transistor
4
causes the bias of the node for a drain of the access transistor
7
and a source of the select transistor
4
to be changed.
Thus, while signal charges are accumulated in the photo diode
6
, potentials at the sources of the reset and select transistors
1
and
4
are changed. At this time, if a row select signal is applied to the gate of the access transistor
7
through a row select signal input terminal
8
, then a potential difference due to the signal charges generated in the photo diode
6
is transferred to a column select line
9
.
After the signal level due to the signal charges generated in the photo diode
6
is detected, the reset transistor
1
is turned on by the reset signal received through the reset signal input terminal
2
and all the signal charges accumulated in the photo diode
6
are reset.
In order to solve the noise problem of the conventional CMOS image sensors of
3
TR pixel structure, a CMOS image sensor of
4
TR pixel structure has been studied and is described as follows.
FIG. 3
is a cross sectional diagram showing a conventional CMOS image sensor of a
4
TR pixel structure and
FIG. 4
is a circuit configuration of the
4
TR pixel structure of the conventional image sensor.
As shown in
FIG. 3
, a p-type epitaxial layer
301
is formed on a p-type semiconductor substrate
300
and an n type well region
302
is formed in a portion of said p-type epitaxial layer
301
.
In a portion of the surface of the p-type epitaxial layer
301
, a photo diode region consists of an n+impurity doped layer
303
in the p-type epitaxial layer
301
and a p+surface impurity layer
307
formed on a surface of the impurity doped layer
303
.
A n+ region
304
is formed in a portion of a p-type epitaxial layer
301
spaced apart from the photo diode region. The n+ region is used as a floating diffusion region for sensing image charges.
Another n+ region
309
is formed in a p type epitaxial layer
301
spaced apart from the n+ region
304
and is connected to a power supply voltage VDD.
A lightly doped n-type impurity layer
308
is formed in a surface of the p-type epitaxial layer
301
between the photo diode region
303
and
307
and the n+ region
304
, and a transfer gate
305
is formed over the lightly doped n-type impurity layer
308
.
Next, a reset gate
306
is formed over the surface of the epitaxial layer
301
between the n+ region
304
and the n+ region
309
.
A circuit configuration and a charge sensing operation of the conventional CMOS image sensor of
4
TR pixel structure will be described as follows by referring to FIG.
4
.
The circuit of
4
TR pixel structure is constructed with a reset transistor
21
, a select transistor
24
, an access transistor
30
, a transfer transistor
29
and a photo diode
27
.
The reset transistor
21
has a gate receiving a reset signal through a reset signal input terminal
22
. One electrode of the reset transistor
21
is connected to a floating node
25
and the other electrode of the reset transistor
21
is connected to a VDD terminal
23
. The select transistor
24
has a gate connected to the floating
Kim Hang Kyoo
Lee Seo Kyu
Shin Jung Soon
Hynix / Semiconductor Inc.
Kang Donghee
Thomas Tom
LandOfFree
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