CMOS I/O circuit with high-voltage input tolerance

Details CMOS I/O circuit with high-voltage input tolerance CMOS I/O circuit with high-voltage input tolerance

1997-06-04

1999-11-23

Santamauro, Jon

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 58, 326 83, H03K 190185

Patent

active

059907053

ABSTRACT:
The invention provides for an input/output circuit in a CMOS integrated circuit which can withstand pad voltages which are higher than the supply voltages for the integrated circuit. The input/output circuit has a pair of first polarity-type transistors which is connected in series between a first supply voltage terminal and the input/output pad, and a pair of second polarity-type transistors which is connected in series between a second supply voltage terminal and the pad. Responsive to a disable control signal, one of the first polarity-type and one of the second polarity-type transistors are turned off. Switch circuitry is connected between the pad and a gate of a second transistor of the second polarity-type transistor pair. The switch circuitry forms an open circuit when the pad voltage is in the range of the supply voltages of the input/output circuit, and forms a closed circuit to connect the gate to the pad when the pad voltage is outside the range of supply voltages so that no conducting path is created through the pair of second polarity-type transistors. This allows the pad to remain in a high impedance state even when the pad voltage is outside the range of supply voltages.

REFERENCES:
patent: 5396128 (1995-03-01), Dunning et al.
patent: 5450025 (1995-09-01), Shay
patent: 5543733 (1996-08-01), Mattos et al.
patent: 5635860 (1997-06-01), Westerwick
patent: 5729157 (1998-03-01), Monk et al.
patent: 5736869 (1998-04-01), Wei

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