CMOS I/O circuit with 3.3 volt output and tolerance of 5 volt in

Electronic digital logic circuitry – Interface – Supply voltage level shifting

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326 21, H03R 190185

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active

055460194

ABSTRACT:
As VLSI chip design migrates from 5 volt designs to lower voltage designs, such as 3.3 volts, interfacing components with different power supplies is an unavoidable issue. This invention provides simple and inexpensive circuits which provide full rail to rail output voltage swing and prevent the PN junctions in the isolation wells of metal oxide semiconductor field effect transistors from becoming forward biased. This prevents excessive leakage currents and component damage which can occur when PN junctions in the isolation wells of PMOS field effect transistors become forward biased.

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