CMOS ECL output buffer

Details CMOS ECL output buffer CMOS ECL output buffer

2001-12-20

2003-05-13

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Interface

Logic level shifting

C326S074000

Reexamination Certificate

active

06563342

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to a CMOS buffer that can be used to couple signals to ECL (emitter coupled logic).
BACKGROUND OF THE INVENTION
An output buffer of an integrated circuit is generally used to transfer signals from the integrated circuit to an output of the integrated circuit, although an output buffer may also include an entire integrated circuit dedicated solely to driving-signal lines. The output of the integrated circuit may be coupled to various wires, cables or traces that may be generally described as electrical transmission lines, especially when the output buffer is driving electrical signals with fast edge rates. In addition, such transmission lines may be coupled to the input terminals of other integrated circuits. In the context of digital signal communications, the varying electrical characteristics of the transmission line, as well as of the downstream circuits supplied by the output buffer, give rise to a number of problems.
For example, ECL typically uses bipolar transistor technology rather than CMOS technology. Therefore, ECL specifications are usually written around bipolar capabilities. While CMOS integrated circuits typically operate with a power supply of 5 V or 3.3 V, ECL traditionally operates with a negative power supply (such as −5 V). Transistors operating at this large negative voltage are less tolerant of total dose radiation. Also, normal ECL output buffer specifications require a low input resistance, whereas CMOS circuits usually operate at higher resistances. Thus, standard ECL is not generally compatible with CMOS circuits. Accordingly, driving an ECL circuit from a CMOS circuit presents difficult design issues.
The present invention is directed to a buffer employing a feedback amplifier that compares the output voltage of the buffer to a desired on-chip reference voltage in order to drive the output high-state voltage of the buffer to a desired level. The feedback amplifier allows the buffer to accurately meet the high-state voltage and output resistance requirements of an ECL circuit.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a CMOS ECL output buffer has a buffer input and a buffer output, and the buffer output is arranged to provide an output signal to an ECL circuit in response to an input signal on the buffer input. The CMOS ECL output buffer comprises a CMOS differential feedback amplifier, a CMOS output circuit, and a negative feedback circuit. The CMOS differential feedback amplifier has a reference input, a feedback input, and an output. The reference input is held at a high-state reference voltage suitable for use as a high state voltage by the ECL circuit. The CMOS output circuit is coupled between the output of the CMOS differential feedback amplifier and the buffer output. The negative feedback circuit is coupled between the buffer output and the feedback input of the CMOS differential feedback amplifier. The output signal has a high state and a low state, and the high-state is at about the high-state reference voltage.
In accordance with another aspect of the present invention, a method of buffering a signal supplied to ECL comprises the following: providing a reference to a CMOS differential amplifier, wherein the reference has a level compatible with an upper voltage of the ECL; controlling the signal supplied to the ECL in response to the CMOS differential amplifier and in response to an input signal; and, providing negative feedback to the CMOS differential amplifier based upon the output signal, wherein the negative feedback causes the CMOS differential amplifier to control the signal supplied to the ECL at a level commensurate with the reference.
In accordance with yet another aspect of the present invention, a CMOS ECL output buffer chip comprises a buffer input, a buffer output, a CMOS differential negative feedback amplifier, a CMOS reference circuit, a CMOS feedback circuit, a CMOS output circuit, and a CMOS input circuit. The buffer input receives an input signal. The buffer output provides an output signal to an ECL circuit. The CMOS differential negative feedback amplifier has a reference input, a feedback input, and an output. The CMOS reference circuit is coupled to the reference input of the differential negative feedback amplifier, and the CMOS reference circuit establishes a high-state reference voltage suitable for use by the ECL circuit. The CMOS feedback circuit is coupled between the buffer output and the feedback input of the differential negative feedback amplifier. The CMOS output circuit is coupled between the output of the CMOS differential negative feedback amplifier and the buffer output. The CMOS input circuit is coupled between the buffer input and the CMOS output circuit. Accordingly, the output signal is low when the input signal is low, and the output signal is at about the high-state reference voltage when the input signal is high.


REFERENCES:
patent: 5089723 (1992-02-01), Davis et al.
patent: 5874837 (1999-02-01), Manohar et al.
patent: 6424217 (2002-07-01), Kwong

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