CMOS ECL input buffer

Details CMOS ECL input buffer CMOS ECL input buffer

2001-12-20

2003-03-18

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Interface

Logic level shifting

C326S073000, C327S089000, C330S253000

Reexamination Certificate

active

06535017

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to a buffer that can be used to couple signals from an ECL (emitter coupled logic) circuit to a CMOS circuit.
BACKGROUND OF THE INVENTION
ECL typically uses bipolar transistor technology rather than CMOS technology. Therefore, ECL specifications are usually written around bipolar capabilities. As part of these specifications, ECL traditionally operates with a negative power supply (such as −5V). On the other hand, CMOS integrated circuits typically operate with a positive power supply (such as 5V or 3.3V). Thus, a standard ECL circuit is not generally compatible with a CMOS circuit without the use of a buffer between the two circuits.
While buffers that transfer signals from one circuit to another are generally known, care must be taken in providing a buffer between CMOS and ECL circuits because the transistors of a buffer operating at a large negative voltage, such as that used by an ECL circuit, are less tolerant of total dose radiation.
The present invention, therefore, is directed to an input buffer to a CMOS circuit that allows the CMOS circuit to accept input signals from an ECL circuit and that is more tolerant of total dose radiation than existing ECL to CMOS buffers. Such a buffer may be part of an integrated circuit, or it may be an entirely separate integrated circuit dedicated solely to driving signal lines.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a CMOS ECL input buffer has a buffer input and a buffer output. The buffer input receives signals from an ECL circuit, and the buffer output provides an output signal to a CMOS circuit in response to the input signal from the ECL circuit. The CMOS ECL input buffer comprises a CMOS differential amplifier, a CMOS input circuit, a reference circuit, and a CMOS output circuit. The CMOS differential amplifier has first and second inputs and an output. The CMOS input circuit is coupled between the buffer input and the first input of the CMOS differential amplifier so as to couple the input signal to the first input of the CMOS differential amplifier. The input signal has an input voltage swing. The reference circuit provides a reference to the second input of the CMOS differential amplifier. The reference is nominally set at substantially a midpoint of the input voltage swing. The CMOS output circuit is coupled between the output of the CMOS differential amplifier and the buffer output so as to provide the output signal to the buffer output. The output signal, in response to the CMOS differential amplifier, swings between a typical CMOS positive source voltage and ground as the input signal traverses the reference.
In accordance with another aspect of the present invention, a CMOS ECL input buffer chip has a buffer input and a buffer output. The buffer input receives signals from an ECL circuit, and the buffer output provides an output signal to a CMOS circuit in response to the input signal from the ECL circuit. The CMOS ECL input buffer chip comprises a CMOS amplifier, first and second p-channel source followers, and a capacitor. The CMOS amplifier has a cross coupled active load, first and second inputs, and an output. The cross coupled load includes a cascode section. The first p-channel source follower couples the buffer input to the first input of the CMOS amplifier. The second p-channel source follower couples a reference to the second input of the CMOS amplifier. The capacitor filters out ground noise due to simultaneous switching of CMOS circuits on the CMOS ECL input buffer chip.
In accordance with yet another aspect of the present invention, a method of buffering a signal between an input ECL circuit and an output CMOS circuit comprises the following: level shifting an input signal up through a p-channel source follower and supplying the level shifted input signal to a first input of a CMOS differential amplifier, wherein the input signal is from the ECL circuit, and wherein the input signal has an input signal swing; level shifting a reference up through a p-channel source follower and supplying the level shifted reference to a second input of the CMOS differential amplifier, wherein the reference is substantially midway in the input signal swing; and, coupling an output of a cross coupled active load of the CMOS differential amplifier to an output terminal connectable to the output CMOS circuit, wherein the cross coupled active load provides a high gain at a balance point between the input signal and the reference.


REFERENCES:
patent: 5332935 (1994-07-01), Shyu
patent: 5469097 (1995-11-01), Ho
patent: 401062017 (1989-03-01), None

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