CMOS dynamic memory device having multiple flip-flop circuits se

Details CMOS dynamic memory device having multiple flip-flop circuits se CMOS dynamic memory device having multiple flip-flop circuits se

1990-09-04

1992-07-21

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365181, 365190, 365233, 307530, G11C 11409

Patent

active

051329301

ABSTRACT:
In a metal-oxide semiconductor (MOS) dynamic formed on a semiconductor substrate, data nodes of a first flip-flop are connected to a first pair of folded bit lines. Its power supply node is connected through a switch to a first power supply (Vss). Data nodes of a second flip-flop are connected to a second pair of folded bit lines. Its power supply node is connected through a switch to the first power supply (Vss). A power supply node of a third flip-flop is connected through a switch to a second power supply (Vcc). Data nodes of the third flip-flop are coupled through a first pair of transfer gates to the first pair of the folded bit lines, and through a second pair of transfer gates to the second pair of the folded bit lines. Coupling the first to the third flip-flops forms a first sense amplifier and coupling the second to the third flip-flops forms a second sense amplifier.

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Denshi Zairya (Electronics Materials), Jan. 1986, pp. 41-42.
IEEE, International Solid State Circuits Conference, Digest of Tech. Papers, ISSCC 84, Session XVIII: 256K/1Mb DRAMS-II; FAM 18.6: pp. 282-283.
"An Experimental 1Mb DRAM with On-Chip Voltage Limiter", Feb. 1984.

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