CMOS dynamic logic structure

Details CMOS dynamic logic structure CMOS dynamic logic structure

1993-06-03

1995-01-03

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 21, H03K 19096, H03K 190948

Patent

active

053789423

ABSTRACT:
A CMOS dynamic logic structure has a plurality of logic gates, and the logic gates includes type-1 and type-3 logic gates alternately connected with each other. Each logic gate is separated into a function unit and a driver unit. The function unit has a PMOS precharge transistor, and a logic tree block stacked with the PMOS precharge transistor. The driver unit has an NMOS evaluation transistor, and the NMOS evaluation transistor and the PMOS precharge transistor of the previous-stage logic gate is controlled by an identical clock in order not to be turned on simultaneously.

REFERENCES:
patent: 4565934 (1986-01-01), Southerland, Jr.
patent: 4700088 (1987-10-01), Tubbs
patent: 4820943 (1989-04-01), Makino et al.
patent: 5291076 (1994-03-01), Bridges et al.

Affiliated with

Also associated with

Rating

CMOS dynamic logic structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS dynamic logic structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS dynamic logic structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2213186