CMOS dynamic logic circuitry using quantum mechanical...

Details CMOS dynamic logic circuitry using quantum mechanical... CMOS dynamic logic circuitry using quantum mechanical...

2000-08-28

2002-04-02

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S095000, C326S119000, C326S134000

Reexamination Certificate

active

06366134

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates, in general, to logic circuitry used in electronic devices, and in particular, to dynamic logic circuitry designed for a Complementary Metal Oxide Semiconductor (CMOS) process including quantum mechanical tunneling structures.
BACKGROUND OF THE INVENTION
The continual demand for enhanced transistor and integrated circuit performance has resulted in improvements in existing devices, such as silicon, bipolar, and Complementary Metal Oxide Semiconductor (CMOS) transistors and Galium Arsenide (GaAs) transistors, and also in the introduction of new device types and materials. In particular, scaling down device sizes to enhance high frequency performance leads to observable quantum mechanical effects, such as carrier tunneling through potential barriers. These effects led to development of alternative device structures which take advantage of such tunneling phenomenon; such as tunneling, and resonant tunneling, diodes and transistors. For ease of reference, all such structures are hereafter collectively referred to as tunneling diodes (TDs).
Tunneling diodes are generally two terminal devices with conduction carriers tunneling through potential barriers to yield current-voltage curves with portions exhibiting negative differential resistance (NDR). This negative differential resistance characteristic has been used as the basis for a wide range of high performance designs.
Conventionally, tunneling and resonant tunneling diodes have been limited in implementation to GaAs and other high performance processes. Conventional methods have focused on building TDs in GaAs for several reasons; mainly because the speed characteristics and small process features of GaAs processes were conducive to tunneling mechanics. However, performance considerations such as difficulty controlling peak current in TDs, limited their practical application and use. Additionally, since GaAs processes were not practical or cost efficient for high-volume, consumer-related production, TDs were generally limited in application to research and developmental applications.
Previously, the feature sizes of standard silicon processes, such as CMOS, were not conducive to producing such tunneling structures. Other conventional methods of utilizing tunneling structures in conjunction with standard silicon processes entailed fabrication of a TD structure in a non-silicon process, followed by transferring and bonding (or electrically coupling) the TD structure to a host silicon substrate. While certain performance issues may have thus been addressed, such a process required extra design time and processing steps. The additional design and fabrication costs associated with these approaches is therefore not commercially viable for large volume logic device production.
Thus, conventional implementations of tunneling structures have been used only in discrete form and niche applications, such as high speed pulse and edge generation; produced in costly, high-performance processes. Limitations to conventional tunneling structures include the difficulty in controlling peak current and the lack of an integrated circuit process capable of commercially producing tunneling structures in a commercially viable format.
In the absence of commercially viable TDs, conventional CMOS logic circuit designs have utilized functional components readily available in the CMOS process, such as inverters and logic and transmission gates. Conventional methods have focused on optimizing the design of these components individually, and improving their efficiency when utilized within larger circuits. Still, such conventional methods inevitably yield device inefficiency; due mainly to layout area, power consumption, and operational speed limits resulting from standard CMOS components.
As performance demands have increased and feature sizes for CMOS processes have decreased, fabrication of tunneling structures in a production CMOS process becomes feasible. Tunnel diode growth on silicon is relatively immature. Recently, CMOS compatible tunnel diodes have been demonstrated to show that a wide range of current densities can be obtained; addressing requirements for imbedded memory and signal processing applications.
Therefore, a system of logic circuitry designs incorporating tunneling structures for a CMOS process is now needed; providing enhanced design performance and efficiency while overcoming the aforementioned limitations of conventional methods.
SUMMARY OF THE INVENTION
Dynamic logic circuitry is used extensively in modern electronics systems and devices. Dynamic logic, being denser and more efficient than static logic implementations typical of CMOS designs, is widely used in demanding high-performance applications. As such, dynamic logic is prevalent in the design of systems such as signal processing units, encoding and decoding devices, and circuitry performing intensive mathematical operations.
In the present invention, dynamic logic circuitry is designed for a CMOS process including quantum mechanical tunneling structures; providing circuit layout area, power consumption, and operational speed advantages over conventional methods. NDR and current-voltage (I-V) characteristics of tunneling structures are exploited to provide high-performance, high functionality logic circuitry. Tunneling structures are utilized, replacing conventional CMOS components, to address MOS leakage and hold data state in dynamic logic circuits.
In one embodiment of the present invention, a dynamic logic network is designed incorporating tunneling diodes. The tunneling diodes replace a number of components used in conventional designs, providing high system performance with optimum design overhead.


REFERENCES:
patent: 4352031 (1982-09-01), Holbrook et al.
patent: 5018107 (1991-05-01), Yoshida
patent: 5903170 (1999-05-01), Kilkarni et al.

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