CMOS driver which uses a higher voltage to compensate for thresh

Electronic digital logic circuitry – Interface – Current driving

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36518905, 326119, 326 21, 327333, 327546, H03K 190948

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active

053999207

ABSTRACT:
The low-power two-stage data output buffer (20,70) includes a two-stage switching circuit (50, 72) that drives an n-channel pull-up transistor (24) in two stages, thus only using current from the pumped high voltage supply during the second stage of the operation. The two-stage switching circuit (50, 72) first drives the pull-up transistor (24) with the supply voltage, V.sub.DD, then drives it with the pumped high voltage supply, V.sub.PP. A feedback circuit, coupled between the output node (28) and the two-stage switching circuit (50, 72), generates a path from the high voltage supply, V.sub.PP, to the n-channel pull-up transistor (24) in response to the supply voltage level appearing on the output node (28), and blocks the path from the high voltage supply, V.sub.PP, to the supply voltage.

REFERENCES:
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patent: 4906056 (1990-03-01), Taniguchi
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patent: 5113087 (1992-05-01), Ueno
patent: 5128560 (1992-07-01), Chern et al.
patent: 5179299 (1993-01-01), Tipon
patent: 5255222 (1993-10-01), Eaton, Jr.
IEEE 1993 Custom Integrated Circuits Conference, "An Adjustable Output Driver With Self-Recovering V.sub.pp Generator For 4M.times.16 DRAM" by K. Furutani, H. Miyamoto, Y. Morooka, M. Suwa and H. Ozaki, pp. 25.3.1-25.3.4.
IEEE, 1992 1992 Symposium on VLSI Circuits Digest of Technical Papers, "Application of a High-Voltage Pumped Supply For Low-Power DRAM" by R. C. Foss, G. Allan, P. Gillingham, F. Larochelle, V. Lines, G. Shimokura, pp. 106-107.

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