CMOS device on ultrathin SOI with a deposited raised...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S347000, C257S353000, C257S379000

Reexamination Certificate

active

06891228

ABSTRACT:
A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer, forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and hearing the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.

REFERENCES:
patent: 5567966 (1996-10-01), Hwang
patent: 5814553 (1998-09-01), Chuang et al.
patent: 6248637 (2001-06-01), Yu
patent: 6287924 (2001-09-01), Chao et al.
patent: 6355962 (2002-03-01), Liang et al.
patent: 6372589 (2002-04-01), Yu
patent: 6403433 (2002-06-01), Yu et al.
patent: 6403434 (2002-06-01), Yu
patent: 20020053711 (2002-05-01), Chau et al.

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