CMOS device integration for low external resistance

Details CMOS device integration for low external resistance CMOS device integration for low external resistance

2007-03-13

2007-03-13

Nadav, Ori (Department: 2811)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S592000, C257S377000, C257S384000

Reexamination Certificate

active

10763308

ABSTRACT:
The present invention relates to a Complementary Metal Oxide Semiconductor (CMOS) device having a lower external resistance and a method for manufacturing the CMOS device. The inventive MOSFET is produced by forming first suicide regions in a substrate as well as atop surface of a gate region and forming second silicide regions where second silicide thickness is greater than the first silicide thickness. The inventive method produces a low resistance first silicide in close proximity to the channel region of the device, where the incorporation of the first silicide decreases the external resistance of the device while the incorporation of the second silicide produces low sheet resistance interconnects.

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