CMOS-compatible non-volatile memory cell with lateral...

Details CMOS-compatible non-volatile memory cell with lateral... CMOS-compatible non-volatile memory cell with lateral...

2007-11-13

2007-11-13

Lee, Calvin (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S258000

Reexamination Certificate

active

11240030

ABSTRACT:
An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

REFERENCES:
patent: 6413818 (2002-07-01), Huang et al.
patent: 7067875 (2006-06-01), Shukuri
patent: 7154779 (2006-12-01), Mokhlesi et al.

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