Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1995-03-09
1999-10-26
Martin-Wallace, Valencia
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257288, 257350, 257351, 257352, H01L 2994
Patent
active
059733632
ABSTRACT:
An integrated circuit comprising an insulating substrate; a layer of silicon formed on said insulating substrate; a p-channel transistor and an n-channel transistor formed in said silicon layer and interconnected in a CMOS circuit; wherein the ratio of transistor p-channel length to transistor n-channel length in the CMOS circuit is less than or equal to one.
REFERENCES:
patent: 3309586 (1967-03-01), Kleinknecht
patent: 3492511 (1970-01-01), Crawford
patent: 4037140 (1977-07-01), Eaton, Jr.
patent: 4072910 (1978-02-01), Dingwall et al.
patent: 4177084 (1979-12-01), Lau et al.
patent: 4183134 (1980-01-01), Oehler et al.
patent: 4198649 (1980-04-01), Berry
patent: 4282556 (1981-08-01), Ipri
patent: 4385937 (1983-05-01), Ohmura
patent: 4418470 (1983-12-01), Naster et al.
patent: 4425700 (1984-01-01), Sasaki et al.
patent: 4463492 (1984-08-01), Maeguchi
patent: 4488230 (1984-12-01), Harrison
patent: 4509990 (1985-04-01), Vasudev
patent: 4523963 (1985-06-01), Ohta et al.
patent: 4588447 (1986-05-01), Golecki
patent: 4607176 (1986-08-01), Burrows et al.
patent: 4615762 (1986-10-01), Jastrzebski et al.
patent: 4617066 (1986-10-01), Vasudev
patent: 4659392 (1987-04-01), Vasudev
patent: 4682055 (1987-07-01), Upadhyayula
patent: 4717836 (1988-01-01), Doyle
patent: 4766482 (1988-08-01), Smeltzer et al.
patent: 4775641 (1988-10-01), Duffy et al.
patent: 4843448 (1989-06-01), Garcia et al.
patent: 4989057 (1991-01-01), Lu
patent: 5027171 (1991-06-01), Reedy et al.
patent: 5141882 (1992-08-01), Komori et al.
patent: 5145802 (1992-09-01), Tyson et al.
patent: 5300443 (1994-04-01), Shimabukuro et al.
patent: 5313077 (1994-05-01), Yamazaki
patent: 5341009 (1994-08-01), Young et al.
patent: 5391903 (1995-02-01), Strater et al.
patent: 5416043 (1995-05-01), Burgener et al.
Betty Prince (Texas Instruments USA); "Semiconductor Memories, A Handbook of Design, Manufacture and Application", Second Edition; Copyright 1983, 1991 by John Wiley & Sons, Ltd., West Sussex, England; title pages; pp. 141-145 and pp. 434-443.
Stanley Wolf, Ph.D. and Richard N. Tauber, Ph.D.; "Silicon Processing for the VLSI Era", vol. 1: Process Technology; Copyright 1986 by Lattice Press, Sunset Beach, California; title pages; pp. 151-155.
Stanley Wolf, Ph.D.; "Silicon Processing for the VLSI Era", vol. 2: Process Integration; Copyright 1990 by Lattice Press, Sunset Beach, California; title pages; pp. 68-83.
"Physics of Semiconductor Devices," S.M. Sze, VLSI Technology, Second Edition, published by John Wiley & Sons, Taipai, Taiwan at 344 and at Sections 8.4.3-8.4.4, at 477-485.
Colinge, Jean-Pierre, Silicon On Insulator Technology: Materials to VLSI, Kluwa Academic Publishers, 1991, at p. 112.
Patent Abstracts of Japan, vol. 008, No. 074 (E-236), Apr. 6, 1984 & JP, A, 58 222573 (Hitachi Seisakusho KK; Others; 01), Dec. 24, 1983.
Search Report dated Jun. 24, 1996, International Application No. PCT/US96/01968.
Patent Abstracts of Japan vol. 007, No. 049 (E-161), Feb. 25, 1983 & JP,A,57 197848 (Tokyo Shibaura Denki KK), Dec. 4, 1982.
Patent Abstracts of Japan vol. 005, No. 159 (E-077), Oct. 14, 1981 & JP,A, 56 090549 (Toshiba Corp), Jul. 22, 1981.
Syed and Abidi, "Gigahertz Voltage-Controlled Ring Oscillator", Electronics Letters, Jun. 5, 1986, vol. 22, No. 12.
Extended Abstracts, vol. 93/1, 1993, Pennington, New Jersey US, pp. 1201-1202, XP000432018 H. Nishizaza et al.: An Advanced Dielectric Isolation Structure for SOI-CMOS/BiCMOS VLSIs.
Chan et al., Comparison of ESD Protection Capability of SOI and Bulk CMOS Output Buffers,1994 IEEE International Reliability Physics Proceedings. pp. 292-298.
J.P. Whitehead and N.N. Duncan, Design and Evaluation of CMOS-SOS On-Chip Input Protection Circuits, Electrostatic Discharge Damage in Electronics Seminar Proceedings (1986) p. 4.2.1-4.2.10.
Cohen & Caswell, An Improved Input Protection Circuit for CMOS/SOS Arrays, IEEE Transactions on Electron Devices, vol. ED 25, No. 8, Aug. 1978, pp. 926-933.
W. Palumbo and M.P. Dugan, Design and Characterization of Input Protection Networks for CMOS/SOS Applications, 1986 Electrical Overstress/Electrostatic Discharge Symposium Proceedings, (1986) pp. 182-187.
Chen et al., "Self-Registered Gradually Doped Source Drain Extension Short Channel CMOS/SOS Devices", IEEE Electron Device Letters, vol. 3, No. 12, Dec. 1982, New York.
R. Reedy et al., "Thin (100 nm) SOS for Application to Beyond VLSI Microelectronics," Materials Research Society Symp. Proc., vol. 107, Nov./Dec. 1988, pp. 365-376.
G. Garcia et al., "High-Quality CMOS in Thin (100 nm) Silicon on Sapphire," IEEE Electron Device Letters, vol. 9, No. 1, Jan., 1988, pp. 32-34.
P.R. de la Houssaye et al., "Fabrication of n-channel metal-oxide-semiconductor field-effect transistors with 0.2 .mu.m gate lengths in 500.ANG. thin film silicon on sapphire," Journal of Vacuum Science & Technology B, vol. 10, No. 6, Nov./Dec. 1992, pp. 2954-2957.
P.H. Woerlee et al., "Half-micron CMOS on Ultra-thin Silicon on Insulator," Technical Digest of the International Electron Devices Meeting, Dec. 3-6, 1989, pp. 821-824.
N. Sasaki et al., "A CMOS/SOS Synchronous Static RAM Fabricated with an Advanced SOS Technology," Japanese Journal of Applied Physics, vol. 18 (1979), Supplements 18-1, pp. 57-62.
T. King et al., "A low-temperature (.ltoreq.550 C) silicon-germanium MOS thin-film transistor technology for large-area electronics," Technical Digest of the International Electron Devices Meeting, Dec. 8-11, 1991, pp. 567-570.
I. Golecki et al., "Recrystallization of silicon-on-sapphire by cw Ar laser irradiation: Comparison between the solid-and the liquid-phase regimes," Applied Physics Letters, 37 (10), Nov. 15, 1980, pp. 919-921.
T. Inoue et al., "Crystalline disorder reduction and defect-type change in silicon on sapphire films by silicon implantation and subsequent thermal annealing," Applied Physics Letters 36 (1) Jan. 1, 1980, pp. 64-67.
I. Golecki et al., "Improvement of crystalline quality of epitaxial silicon-on-sapphire by ion implantation and furnace regrowth," Solid-State Electronics, vol. 23, pp. 803-806.
J. Linnros et al., "Ion-beam-induced epitaxial regrowth of amorphous layers in silicon on sapphire," The American Physical Society, vol. 30(7), Oct. 1, 1984, pp. 3629-3638.
S. Lau et al., "Improvement of crystalline quality of epitaxial Si layers by ion-implantation techniques," Applied Physics Letters, 34 (1) Jan. 1, 1979, pp. 76-78.
S.M. Sze, Physics of Semiconductor Devicies, Second Edition, John Wiley & Sons, Taipei, Taiwan, Sections 8.4.3-8.4.4 at p. 344, 477-485.
R. Reedy et al., "Characterization of Defect Reduction and Aluminum Redistribution in Silicon Implanted SOS Films," Journal of Crystal Growth, North-Holland Publishing Co., vol. 58, No. 1, Jun. 1982, pp. 53-60.
R.E. Reedy et al., "Characterization of Defect Reduction and Aluminum Redistribution in Silicon Implanted SOS Films", Journal Of Crystal Growth, vol. 58, No. 1, pp. 53-60, Jun. 1982.
R.E. Reedy et al., "Suppressing A1 Outdiffusion in Implantation Amorphized and Recrystallized Silicon on Sapphire Films", Applied Physics Letters. vol. 42, No. 8, pp. 707-709, Apr., 1983.
G.A. Garcia et al., "High-Quality CMOS on Thin (100 nm) Silicon on Sapphire", IEEE Electron Device Letters, vol. 9, No. 1, pp. 32-34, Jan. 1988.
R.E. Reedy et al., "Thin (100 nm) SOS for Application to Beyond VLSI Microelectronics", Mat. Res. Soc. Symp. Proc., vol. 107, pp. 365-376, 1988.
P.R. de la Houssaye, et al., "Fabrication of n-channel metal-oxide-semiconductor field-effect transistors with 0.2.mu.m gate lengths in 500 .ANG.thin film silicon on sapphire", Journal of Vacuum Science and Technology: Part B, vol. 10, No. 6, pp. 2954-2957, Nov./Dec. 1992.
P.H. Woerlee, et al., "Half-Micron CMOS on Ultra-Thin Silicon on Insulator", Technical Digest of the International Electron Devices Meeting 1989, Washington, D.C., pp. 821-824, Dec. 3-6, 1989.
Nobuo Sasaki et al., "A CMOS/SOS Synchronous Static RAM Fabricated with an Advanced SOS Technology", Japanese Journal of Applied Physics, Supplement 18-1, vol. 18, pp. 57-62, 1979.
Adele E. Schmitz et al., "A Deep-Submicromete
Burgener Mark L.
Greene Richard M.
Reedy Ronald E.
Staab David R.
Martin-Wallace Valencia
Peregrine Semiconductor Corp.
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