CMOS circuit technique for improved switching speed of single-en

Details CMOS circuit technique for improved switching speed of single-en CMOS circuit technique for improved switching speed of single-en

1998-12-08

2000-05-30

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 17, H03K 19096

Patent

active

060694963

ABSTRACT:
A method and apparatus for improving the forward path switching speed of a complementary CMOS inverter is presented. A large P-type to N-type FET ratio is used to tune the inverter trigger point to the falling edge of the input signal to the inverter. The high P-type to N-type ratio is made feasible by adding a precharge assist pull-down transistor in parallel on the output node of the inverter.

REFERENCES:
patent: 4488066 (1984-12-01), Shoji
patent: 4577124 (1986-03-01), Koike
patent: 5612638 (1997-03-01), Lev
patent: 5818264 (1998-10-01), Ciraula et al.
patent: 5841300 (1998-11-01), Murabayashi et al.

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