CMOS circuit having a reduced tendency to latch

Details CMOS circuit having a reduced tendency to latch CMOS circuit having a reduced tendency to latch

1986-07-30

1988-03-01

James, Andrew J.

357 42, 357 231, 357 232, 357 91, H01L 2916, H01L 29163, H01L 2978

Patent

active

047289988

ABSTRACT:
The tendency of a CMOS circuit to latch up is reduced by implanting ions of germanium or tin into the source and drain regions of the circuit. The low energy gap of these ions lowers the band gap of the source and drain regions, which in turn inhibits their ability to inject carriers into the substrate and well.

REFERENCES:
patent: 3242018 (1966-03-01), Grabmaier et al.
patent: 3725145 (1973-03-01), Maki
patent: 4035665 (1977-07-01), Borel et al.
patent: 4111719 (1978-09-01), Mader et al.
patent: 4302875 (1981-12-01), Satou et al.
patent: 4485550 (1984-12-01), Koeneke et al.
Milnes & Feucht, Heterojunctions and Metal-Semiconductor Junctions, Academic Press, N.Y., 1972.

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