CMOS circuit for improved power-on reset timing

Details CMOS circuit for improved power-on reset timing CMOS circuit for improved power-on reset timing

1994-12-08

1996-11-26

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327198, H03L 700

Patent

active

055789510

ABSTRACT:
A power-on reset circuit includes a discharger for applying a negative voltage to the gate of a transistor and quickly discharging a first intermediate signal during a power-off state to thereby generate a stable power-on reset signal even in fast switching of a power supply voltage, and a delay and buffer for maintaining the power-on reset signal at a first constant voltage for a predetermined time.

REFERENCES:
patent: 4970408 (1990-11-01), Hanke et al.
patent: 4983857 (1991-01-01), Steele
patent: 5278458 (1994-01-01), Holland et al.
patent: 5323067 (1994-06-01), Shay

Affiliated with

Also associated with

Rating

CMOS circuit for improved power-on reset timing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS circuit for improved power-on reset timing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS circuit for improved power-on reset timing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1975938