Electronic digital logic circuitry – Signal sensitivity or transmission integrity
Patent
1993-09-15
1995-01-10
Hudspeth, David R.
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
361 91, 326 68, 326121, 327534, 327546, H03K 19003
Patent
active
053810562
ABSTRACT:
A CMOS buffer circuit includes a p-channel MOS transistor having a source terminal connected to an operating voltage source and a substrate terminal connected to a pump voltage source. A first n-channel MOS transistor is connected in series with the p-channel MOS transistor and has a source terminal connected to a reference potential and a drain terminal connected to an output terminal. A second n-channel MOS transistor is connected between and in series with the p-channel MOS transistor and the first n-channel MOS transistor. The second n-channel MOS transistor has a gate terminal connected to the pump voltage source.
REFERENCES:
patent: 4039869 (1977-08-01), Goldman et al.
patent: 4441035 (1984-04-01), Demetrion
patent: 4473758 (1984-09-01), Huntington
patent: 4723081 (1988-02-01), Akatsuka
patent: 4806801 (1989-02-01), Argade et al.
patent: 5057715 (1991-10-01), Larsen et al.
patent: 5300824 (1994-04-01), Iyengan
IEEE Journal Of Solid-State Circuits, vol. 23, No. 3, Jun. 1988, New York (US) pp. 816-819 Pribyl et al. "CMOS Output Buffers for Megabit DRAM's".
Greenberg Laurence A.
Hudspeth David R.
Lerner Herbert L.
Siemens Aktiengesellschaft
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