CMOS buffer circuit

Details CMOS buffer circuit CMOS buffer circuit

2001-06-13

2002-09-10

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S086000, C326S112000, C326S119000, C326S121000

Reexamination Certificate

active

06448814

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit. More particularly, the present invention relates to a complementary metal oxide silicon (CMOS) buffer circuit.
2. Description of the Related Art
CMOS buffer circuits are mainly used for driving devices connected to an output stage thereof, particularly, devices having capacitance. If a signal bus in a memory has to drive a large load, or a clock signal has to drive a large load within a chip in a circuit only formed of logic devices, buffer circuits are needed for the bus signal and the clock signal.
In the case of CMOS very large scale integration (CMOS VLSI), as the integration density increases, capacitance load on the clock signal becomes larger, and particularly in the case of a data output buffer, a load capacitor located outside the chip must be driven. However, the power consumption of the buffer circuit for the bus signal or the clock signal to drive a large load capacitance takes a very large part of entire power consumption of the chip.
Generally, the power consumption of the CMOS circuit can be divided into dynamic power consumption and short circuit power consumption. The dynamic power consumption is inevitable due to the electric characteristics of the CMOS buffer circuit, but the short circuit power consumption results in unnecessarily wasted power. Accordingly, it is preferable to eliminate the short circuit power consumption.
FIG. 1
illustrates a circuit diagram showing a conventional CMOS buffer circuit, and
FIG. 2
illustrates a waveform diagram of signals in the conventional buffer circuit illustrated in
FIG. 1
when it is being driven.
Referring to
FIG. 1
, the conventional CMOS buffer circuit includes a plurality of inverters connected in series, and each of the inverters sequentially increases the output driving ability, so that the inverters are designed to finally drive a large capacitance.
However, in the conventional CMOS buffer circuit illustrated in
FIG. 1
, there is a regular time interval, in which a PMOS transistor (M
11
) and an NMOS transistor (M
12
) turn on at the same time due to a gradual voltage slope with respect to time of a signal N
1
for driving two transistors (M
11
and M
12
). The voltage slope of the signal becomes more gradual as the driven load becomes larger, so that the interval in which the two transistors turn on at the same time becomes longer. During this interval, a short circuit current flows through both the PMOS transistor (M
11
) and the NMOS transistor (M
12
). The size of two transistors (M
11
and M
12
) is generally very large. Thus, the short circuit current corresponding to the two transistors is considerably large.
Referring to
FIG. 2
, a time interval t
1
and a time interval t
2
are intervals in which the two transistors (M
11
and M
12
) are on at the same time, and show that a considerable current flows depending on the size of the two transistors (M
11
and M
12
). In the time interval t
1
, in which a signal N
1
is in transition from a high “H” state to a low “L” state, a regular current unnecessarily flows in the NMOS transistor (M
12
). In the same way, in the time interval t
2
, in which the signal N
1
is in transition from the “L” state to the “H” state, an unnecessary current flows in the PMOS transistor (M
11
).
SUMMARY OF THE INVENTION
To solve the above problems, it is a feature of an embodiment of the present invention to provide a CMOS buffer circuit for preventing unnecessary short circuit current.
Accordingly, to provide the above feature, there is provided a CMOS buffer circuit including a pre-driving stage, an output buffer driving stage, and an output stage.
The pre-driving stage is formed of an even number of inverters, and each of the inverters is preferably designed to make the output driving capability of input signals increase exponentially.
The output buffer driving stage includes a pull-up PMOS driving stage and a pull-down NMOS driving stage. The pull-up PMOS driving stage drives a pull-up PMOS transistor of the output stage, and the pull-down NMOS driving stage drives a pull-down NMOS transistor of the output stage. Since the output signals of the pull-up PMOS driving stage and pull-down NMOS driving stage have the same frequency, and the duty cycle of the pulses are differently devised, an interval in which the pull-up PMOS transistor and pull-down NMOS transistor of the output stage turn on at the same time is prevented.
The output stage is an inverter formed of the pull-up PMOS transistor and pull-down NMOS transistor, and drives a load connected to the output of the inverter.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.


REFERENCES:
patent: 5329175 (1994-07-01), Peterson
patent: 5656960 (1997-08-01), Holzer
patent: 5672983 (1997-09-01), Yamamoto et al.
patent: 6169421 (2001-01-01), Bryan et al.

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