CMOS boosting circuit utilizing ferroelectric capacitors

Details CMOS boosting circuit utilizing ferroelectric capacitors CMOS boosting circuit utilizing ferroelectric capacitors

2001-05-24

2002-08-06

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S145000, C365S230060, C326S088000

Reexamination Certificate

active

06430093

ABSTRACT:

BACKGROUND OF THE INVENTION
Desirable power supply voltages are becoming lower and lower, tending towards three volts and even lower in some recent applications. The challenge that faces designers of ferroelectric memories is to design solutions that allow the memory cell transistors to operate in the saturation region even at these very low voltages. While advances have been made in ferroelectric thin film technology to enable these ferroelectric materials to operate at low power supply voltages, corresponding advances in ferroelectric memory circuit designs are required as well.
A typical two transistor, two capacitor (“2T/2C”) ferroelectric memory cell
10
is shown in FIG.
1
. Ferroelectric memory cell
10
includes two ferroelectric capacitors Z
1
and Z
2
and two N-channel transistors M
1
and M
2
. A word line
12
is coupled to the gates of transistors M
1
and M
2
, and plate line
14
is coupled to the bottom electrode of ferroelectric capacitors Z
1
and Z
2
. The top electrodes of ferroelectric capacitor Z
1
and Z
2
are coupled to the source/drains of each of transistors M
1
and M
2
. Two complementary bit lines
16
and
18
are coupled to the other source/drains of each of transistors M
1
and M
2
. Non-volatile data is stored as a complementary polarization vector in ferroelectric capacitors Z
1
and Z
2
. A typical one transistor, one capacitor (“1T/1C”) ferroelectric memory cell
20
is shown in FIG.
2
. Ferroelectric memory cell
20
includes a ferroelectric capacitor Z
3
and an N-channel transistor M
3
. A word line
22
is coupled to the gate of transistor M
3
, and a plate line
24
is coupled to the bottom electrode of ferroelectric capacitor Z
3
. The top electrode of ferroelectric capacitor Z
3
is coupled to the source/drain of transistor M
3
. A bit line
26
is coupled to the other source/drains of transistors M
3
. Non-volatile data is stored as a polarization vector in ferroelectric capacitors Z
3
.
To ensure the proper operation of ferroelectric random access memory (“FRAM”) technology at low power supply voltages, in either a 1T/1C or 2T/2C architecture, the most critical point for retaining data in the ferroelectric capacitors is to make sure that the data that is written to the cell is at the full supply potential. It is also desirable that the word line be boosted to compensate for the body-effected voltage (VTN) drop of transistors M
1
, M
2
, and M
3
, which is accomplished only if the word line is driven above the VDD power supply voltage by a voltage of at least VTN.
What is desired, therefore, is a ferroelectric boost circuit for use in either 1T/1C or 2T/2C ferroelectric memory architectures so that none of the limited power supply voltage is lost and the full power supply voltage is written to each ferroelectric memory cell.
SUMMARY OF THE INVENTION
According to the present invention, a NAND-INVERT circuit is used to control one electrode of a ferroelectric boosting capacitor. The other node of the capacitor is connected to the node to be boosted, which may be coupled to a word line. The NAND circuit has two inputs, one being coupled to the word line or other node to be boosted and another for receiving a timing signal. The timing input rises to initiate the boosting operation, and falls to initiate the removal of the boosted voltage. Only the selected word line in the memory array is affected as any word line remaining at a low logic level “
0
” will keep the inverter output clamped low. A second embodiment adds a second N-channel transistor in series with the inverter's N-channel transistor to allow for the option of floating the inverter output if it is desired to more quickly drive the word line high during its first upward transition.
It is an advantage of the boost circuit of the present invention that it provides a relatively simple circuit and approach for boosting the word line in a ferroelectric memory array without any loss of marginality at low operating voltage. It is a further advantage of the boost circuit of the present invention that it is compatible with any CMOS process, at any practical supply level. Boosting the word line insures that, when an NMOS access device is used, a full VDD restore voltage is realized for the “1” polarization state when writing a new state or restoring the previously read state. A full VDD restore improves data retention reliability.
It is a further advantage of the boost circuit of the present invention that the circuit is inherently easy to use in that only one timing signal is required.
It is a further advantage of the boost circuit of the present invention that the inverter output is guaranteed to go fully from ground or the negative power rail to the positive power rail, thus ensuring that the maximum possible voltage is available for boosting.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention, which proceeds with reference to the accompanying drawings.


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