Data processing: structural design – modeling – simulation – and em – Emulation
Reexamination Certificate
2006-05-16
2006-05-16
Ferris, Fred (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Emulation
C703S024000, C703S025000, C712S222000
Reexamination Certificate
active
07047179
ABSTRACT:
Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.
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Beausoleil William F.
Ng Tak-kwong
Roth Helmut
Tannenbaum Peter
Tomassetti N. James
Ferris Fred
Orrick Herrington & Sutcliffe LLP
Quickturn Design Systems Inc.
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