Reexamination Certificate
1996-10-30
2001-08-21
Nguyen, Than (Department: 2187)
Reexamination Certificate
active
06276844
ABSTRACT:
TECHNICAL FIELD
The present invention relates to data processing systems, and more particularly to an improved method and apparatus for the arrangement and interconnection between electronic devices to improve system cycle time.
SUMMARY OF THE INVENTION
The present invention provides an arrangement between a plurality of memory storage devices and a memory control unit, which in turn connect to a data processing unit(s). The design is particularly useful for memory storage devices utilizing a synchronous interface. For the purposes of describing the invention we will refer to so called Synchronous Dynamic Random Access Memory storage devices (SDRAMs). The invention is shown in the context of a data processing system, with a data processing unit and a plurality of memory storage units, controlled by a synchronous memory and processor control unit. The said arrangement provides for high speed synchronous data transfer between the memory control unit (MCU) and the memory storage devices (SDRAMs), for frequencies of 75 MHz and higher. The said arrangement utilizes a closely packed structure, branched, balanced hierarchical circuit card wiring, and an intermediate set of buffers or registers between the MCU and the SDRAMs.
Thus coming out of the MCU is an address/control bus and a data bus. The address control bus is uni-directional, from the MCU to the SDRAMs. The data bus is bi-directional. The SDRAMs are arranged on small circuit cards called SIMMs or DIMMs (Single or Double Inline Memory Modules), in a particular configuration to be described. The SDRAMs on the SIMMs are arranged in banks. A SIMM may contain one or more banks of SDRAMs. SDRAMs in separate banks share data lines which pass through a SIMM connector into which the SIMM may be placed. In this invention we describe a SIMM with 18 SDRAMs, arranged in two banks of 9 per side, in a line. We identify 3 groups of 3 SDRAMs per side, with SDRAMs in a group adjacent each other. Preferably the SDRAMs on the second side of the SIMM are so called reverse lead (from the SDRAMs on the 1st side of the SIMM), so that connections to SDRAMs on either side of the SIMM lie atop one another.
Most of the address and control signals to the SDRAMs pass through a buffer which may be optionally registered to a clock. The buffers are located adjacent to the SIMM connectors, near the center of the connector. Signal lines from the buffers preferably go to not more than 2SIMM connectors, to minimize line loading and signal delay. The circuit card wire connections to the buffer are branched, balanced, hierarchical transmission lines which start from a single low impedance line, preferably of order 50 ohms. If there are two SIMM connectors the line preferably splits at or near the center of two adjacent connectors, into two lines of similar impedance and length. After entering the SIMM card the lines split again. In our case with 18 SDRAMs per SIMM. the line preferable splits into 3 lines of similar or higher impedance. The lines again should be of similar or equal length, and terminate with a via, described below, at the center of a group of 3 SDRAMs on either side of the SIMM. The groups of 3 adjacent SDRAMs on either side of the SIMM are connected together with high impedance transmission lines, preferably 80 ohms or higher. The two groups are connected together with the said via at or near the center of these lines.
On either side of the address/control buffers and also adjacent to the SIMM connectors are located data buffers which are preferably registered to a clock. SIMM connectors are preferably placed on either side of the row of buffers, in a symmetric fashion. The group of adjacent SIMM connectors and buffers we call a cluster. The SIMMs themselves may be present or absent from the memory system, but the buffers and connectors remain present. Only one bank of SDRAMs may place data or retrieve data from the data buffers at one time. The connections between the data buffers and the SDRAMS are also preferably branched, balanced transmission lines. For high speed operation we suggest that no more than 4 banks be connected to a single data buffer input. We will describe a set of 8 banks of SRAMs, on 4 SIMM cards. There are 2 SIMM connectors on either side of the row of buffers. To handle this case we use a 2 to 1 multiplexing, registered bi-directional buffer. This device combines two data busses, one for each set of 4 banks of SDRAMs, to a single data bus connected to the MCU. For lower speed operation a simple bi-directional registered data buffer may be used.
Certain signals, from the MCU to the SDRAMs, control which bank in a cluster is active. If, for example, there are 16 banks of SDRAMs sharing a common data bus to the MCU, then there may be 16 unique signals from the MCU, to control which bank is accessing the data bus. Buffers, preferably registered, for these bank select (BS) signals are located preferably in the center of the clusters. Signals from these buffers then go to the chip-select (CS) inputs of the SDRAMs, again in a branched, balanced, hierarchical fashion as described for the address/control signals to the SDRAMs.
The SDRAMs, registers, and MCU are synchronized to a block. The distribution of this reference clock to the many SDRAMs, which may be present or absent, is a problem we address. In our preferred embodiment two groups of 3 SDRAMs on opposite of the a SIMM are connected together, in a fashion similar to one of the 3 legs of the address/control net of a SIMM. We also show a second arrangement of 9 SDRAMs, all on one side of a SIMM, connected to a single clock in a manner similar to the bank select line. These clock signals are preferably terminated with resistive connections to power and ground, with resistors located as close as possible to the SIMM connectors. In our preferred embodiment they are located between the data buffers and the SIMM connectors. This arrangement allows for all components to be mounted on the same side of the base circuit card that contains the SIMM connectors.
It is therefore an object of the present invention to provide an arrangement of a plurality of memory storage devices, a set of intermediate buffers or registers, and a memory control unit, to allow for high speed synchronous transfer of data between the memory control unit and the memory storage devices.
It is yet another object of the invention to provide an arrangement for one or more data processing units which also interface through the memory control unit, and to each other through a processor control unit.
It is yet another object of the invention to provide improved signal quality in the system.
It is yet another object of the invention to reduce the disturbance to the signal quality of the as the number of memory storage devices is varied.
It is yet another object of the invention to minimize the number of intermediate buffers in a fully populated system.
It is yet another object of the invention to provide for high speed transfer to a large number of memory storage devices.
These, and other, objects and advantages of the present invention will now be described, with reference to the following drawings, in which:
REFERENCES:
patent: 4021784 (1977-05-01), Kimlinger
patent: 5053951 (1991-10-01), Nusinov
patent: 5151374 (1992-09-01), Wu
patent: 5283877 (1994-02-01), Gastinel et al.
patent: 5293603 (1994-03-01), MacWilliams et al.
patent: 5333293 (1994-07-01), Bonella
Coteus Paul William
Genz Ralph Herman
Lanzetta Alphonso P.
Maule Warren Edward
Phipps Daniel Julius
Beck Thomas A.
International Business Machines - Corporation
Morris Daniel
Nguyen Than
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