Cluster-wide system clock in a multi-tiered full-graph...

Details Cluster-wide system clock in a multi-tiered full-graph... Cluster-wide system clock in a multi-tiered full-graph...

2011-04-05

2011-04-05

Connolly, Mark (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of plural processors

C713S400000, C713S500000, C713S600000

Reexamination Certificate

active

07921316

ABSTRACT:
Mechanisms for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.

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