Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2008-10-01
2011-11-08
Nguyen, Ha Tran T (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S679000, C204S298010, C257SE21169
Reexamination Certificate
active
08053364
ABSTRACT:
This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with metal oxide deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of a desired electrical property as a function of cathode voltage used during a sputtering process that uses a biased target. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials (e.g., metals and oxygen source), be fabricated to have minimal leakage or “off” current characteristics (Ileakor Ioff, respectively) or a maximum ratio of “on” current to “off” current (Ion/Ioff).
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Chiang Tony
French Wayne
Kumar Pragati
Phatak Prashant
Intermolecular, Inc.
Nguyen Ha Tran T
Scarlett Shaka
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