Clocktree tuning shims and shim tuning method

Details Clocktree tuning shims and shim tuning method Clocktree tuning shims and shim tuning method

2004-02-24

2008-03-18

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07346873

ABSTRACT:
A digital storage medium for storing electronic data for use with a clock tree design tool to design a clock distribution network within an integrated circuit. The electronic data implements a library of shim cells, wherein each of the shims cells represents a physical embodiment of a different clock driver cell such that all of the shim cells in the library are interchangeable in the clock distribution design without requiring any change in the placement or routing within the integrated circuit to maintain compliance with design requirements for the integrated circuit. Each cell within a library represents a structure that introduces a particular delay time in the clock signal. The library contains cells having a range of delays that span a range that is sufficiently large to deal with the range of clock skews typically encountered during integrated circuit design.

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Kourtev, I. and Friedman, E., “Simultaneous Clock Scheduling and Buffered Clock Tree Synthesis”, IEEE International Symposium on Circuits and Systems, Jun. 9-12, 1997.

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