Clocking to support interface of memory controller to external S

Details Clocking to support interface of memory controller to external S Clocking to support interface of memory controller to external S

2000-03-17

2000-12-19

Hoang, Huan

Static information storage and retrieval

Addressing

Sync/clocking

365154, G11C 800

Patent

active

061635022

ABSTRACT:
A network interface device is provided with a memory controller to control data writing and reading to and from an external synchronous SRAM. An interface to the SRAM has a clock pad responsive to an internal clock signal to produce a SRAM clock sent to the SRAM as a reference clock to support access to the SRAM. The clock pad contains an inverter for inverting the internal clock signal so as to produce the SRAM clock in response to the inverted internal clock signal. As a result, read time allocated for reading data from the SRAM to the memory controller is made longer than a cycle of the internal clock signal.

REFERENCES:
patent: 5687134 (1997-11-01), Sugawara et al.
patent: 6034901 (2000-03-01), Toda

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