Clocking systems and methods for pipelined self-timed dynamic lo

Details Clocking systems and methods for pipelined self-timed dynamic lo Clocking systems and methods for pipelined self-timed dynamic lo

1992-05-19

1995-07-18

Bowler, Alyssa H.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 97, H03K 1900

Patent

active

054345200

ABSTRACT:
Clocking systems and methods of the present invention use two or more different clock signals for respective groups or stages of self-timed dynamic (or mousetrap) logic gates. Each clock signal defines a precharging time interval and an evaluation time interval for its respective group or stage of self-timed dynamic logic gates. Using the two or more different clock signals, pipelining of the groups or stages of the self-timed dynamic logic gates can be performed.

REFERENCES:
patent: 3755689 (1973-08-01), Elmer et al.
patent: 4841174 (1989-06-01), Chung et al.
patent: 4949249 (1990-08-01), Lefsky et al.
patent: 5121003 (1992-06-01), Williams
patent: 5208490 (1993-05-01), Yetter

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