Clocking scheme for latching of a domino output

Details Clocking scheme for latching of a domino output Clocking scheme for latching of a domino output

1995-01-04

1995-09-26

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 94, 327211, H03K 19096

Patent

active

054537088

ABSTRACT:
A clocking scheme provides for an improved latching of an output from a domino circuit by delaying a precharging of a domino node. The precharging delay is achieved by introducing the delay in the clocking circuitry which activates the precharging of the domino node. No delay is introduced in the data path in order not to delay the evaluation and transmission of the data signal. During one phase of a clocking cycle, the domino node is precharged to a predetermined logic state. Also during this precharge phase, an input latch couples an input data signal to the domino circuit. During the other phase of the clocking cycle, the domino circuit performs a logic operation based on the input signal. Also during this evaluation phase, an output latch latches the logic state of the domino output for transmission from the output latch. Subsequently, when the precharging phase commences, the precharging of the domino node is delayed until the output latch is completely deactivated, thereby ensuring that the precharge is not latched out to corrupt the data being transmitted.

REFERENCES:
patent: 4568842 (1986-02-01), Koike
patent: 4841174 (1989-06-01), Chung
patent: 4893034 (1990-01-01), Tamura
patent: 4929850 (1990-05-01), Breuninger
patent: 5189319 (1993-02-01), Fung
patent: 5208489 (1993-05-01), Houston
"The Metaflow Architecture", IEEE Micro., by Val Popescu, Merle Schultz, John Spracklen, Gary Gibson, Bruce Lightner and David Isaman, 1991.

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