Clocking scheme for digital signal processor system

Details Clocking scheme for digital signal processor system Clocking scheme for digital signal processor system

1997-09-16

1999-07-13

Heckler, Thomas M.

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

G06F 104

Patent

active

059220767

ABSTRACT:
A digital signal processing system includes a cluster of processors and a host. A host can access each of the processors through an external bus system that interconnects the host with each of the processors. An external port of each of the processors operates at one of a local clock frequency and host clock frequency, the local clock frequency and host clock frequency being asynchronous with one another. The host operates at the host clock frequency. Upon a host access of one of the processors, the clock frequency of operation of the external parallel port of each processor automatically is controlled to operate at the host clock frequency. In an embodiment, each processor also includes a core processor that operates at a core clock frequency that is a multiple of the local clock frequency, asynchronous with the host clock frequency. Thus, the speed of operation of the core processor and that of the external parallel port can be optimized independently.

REFERENCES:
patent: 5611075 (1997-03-01), Garde
patent: 5619720 (1997-04-01), Garde et al.
patent: 5685005 (1997-11-01), Garde et al.

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