Clocking mechanism for delay, short path and stuck-at testing

Details Clocking mechanism for delay, short path and stuck-at testing Clocking mechanism for delay, short path and stuck-at testing

1995-02-21

1997-04-01

Nguyen, Hoa T.

Excavating

371 62, H04B 1700

Patent

active

056174268

ABSTRACT:
In a level sensitive scan design (LSSD) circuit embodiment for testing the behavior of logic circuits, a mechanism is provided for generating a skewed load of data into a set of shift register scan string latches. The nature of the input scan string assures that a certain number of 0 to 1 or 1 to 0 transitions occurs as an input to the block of logic being tested. Furthermore, a mechanism for delaying by one system clock cycle time the capture of information from the logic block in a second shift register scan string provides a mechanism for testing for the occurrence of short paths and long paths while preserving testability for stuck-at faults. Furthermore, all of these advantages are achieved without impacting the traditional stuck-fault test capabilities of the level sensitive scan design methodology.

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