Clocked logic gate circuit

Details Clocked logic gate circuit Clocked logic gate circuit

2000-09-11

2001-12-25

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000, C326S115000

Reexamination Certificate

active

06333645

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a clocked logic gate circuit in which speedup and facility are realized.
For a prior example of a logic gate circuit, a clocked cascade voltage switch logic circuit (CVSL) (hereinafter called clocked CVSL) is known which is described at pages 144 and 145 of “Principle of CMOS VLSI Design: A Systems Perspective” supervised and translated by Tomisawa and Matsuyama and published by Maruzen Co., Ltd. (1988), which is translation of the original publication of the same title by Neil H. E. Weste & Karman Eshraghian.
FIG. 3
shows the above circuit.
The above clocked CVSL is the same as two domino gates operated by true inputs and their complementary inputs with a minimized logic tree. This type logic is superior to a domino logic in that merely a logic with an arbitrary logical expression can be generated and a complete logic family can be constituted. The above logic is superior to a complementary metal-oxide semiconductor (CMOS) logic circuit and a path transistor logic circuit in terms of high speed.
SUMMARY OF THE INVENTION
However, such priority is realized at the cost of excessive wirings, and an effective area which result from its operating with pairs of mutually complementary inputs and at the cost of complexity accompanying a double rail logic.
The object of the present invention is to provide a logic gate circuit which is simpler and easier to use than a double rail logic, and operates at a higher speed than a CMOS logic circuit and a path transistor logic circuit.
The above object is achieved by a circuit which comprises a first load unit (Z
2
) which is provided between the first electric potential and the first node, and charges the first node to the second electric potential, in response to a signal (N); the second load unit (Z
1
) which is provided between the first electric potential and the second node, and charges the second node to the third electric potential, in response to the above signal; a switch circuit (SW) provided among the first node, the second node and the third node; and a drive circuit (DV) which is provided between the above third node and the fourth electric potential, and drives the above switch circuit, in response to the above signal, wherein the above switch circuit comprises a logic circuit (NB) which is provided between the above first node and the above third node, and electrically connects the first node and the third node, in response to an input signal; and a reference field effect transistor (FET) (QNB) which has its source-drain path formed between the above second node and the above third node, and its gate connected to the above first node.


REFERENCES:
patent: 5291076 (1994-03-01), Bridges et al.
patent: 5373203 (1994-12-01), Nicholes et al.
patent: 8-307243 (1996-11-01), None
Weste et al., “Principle of CMOS VLSI Design: A Systems Perspective”, 1988, pp. 144-145.

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